Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33457
Change subject: sb/amd/sr5650: Use 32 bit integers when disabling ports ......................................................................
sb/amd/sr5650: Use 32 bit integers when disabling ports
This function attempts to set bits in the 20s of state and state_save, which won't work since those variables are only 16 bits wide. Extend them to 32 bits to capture all the bit operations.
Change-Id: I5616a2d879a85ff5f57af5af20384516659c62d6 Signed-off-by: Jacob Garber jgarber1@ualberta.ca Found-by: Coverity CID 1347384 --- M src/southbridge/amd/sr5650/pcie.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33457/1
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index f87fadb..6c42fdd 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -59,11 +59,11 @@ { printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port); u32 reg; - u16 state_save; + u32 state_save; uint8_t i; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - u16 state = cfg->port_enable; + u32 state = cfg->port_enable;
if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) state &= AtiPcieCfg.PortDetect;
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33457 )
Change subject: sb/amd/sr5650: Use 32 bit integers when disabling ports ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33457 )
Change subject: sb/amd/sr5650: Use 32 bit integers when disabling ports ......................................................................
sb/amd/sr5650: Use 32 bit integers when disabling ports
This function attempts to set bits in the 20s of state and state_save, which won't work since those variables are only 16 bits wide. Extend them to 32 bits to capture all the bit operations.
Change-Id: I5616a2d879a85ff5f57af5af20384516659c62d6 Signed-off-by: Jacob Garber jgarber1@ualberta.ca Found-by: Coverity CID 1347384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33457 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/southbridge/amd/sr5650/pcie.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index f87fadb..6c42fdd 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -59,11 +59,11 @@ { printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port); u32 reg; - u16 state_save; + u32 state_save; uint8_t i; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - u16 state = cfg->port_enable; + u32 state = cfg->port_enable;
if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) state &= AtiPcieCfg.PortDetect;
-
Jacob Garber (Code Review) -
Patrick Georgi (Code Review)