Patch merged into coreboot/master: 9dccf1c uart: pass register width in the coreboot table

the following patch was just integrated into master:
commit 9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa
Author: Vadim Bendebury 
Date:   Fri Jan 9 16:54:19 2015 -0800

uart: pass register width in the coreboot table

Some SOCs (like pistachio, for instance) provide an 8250 compatible
    UART, which has the same register layout, but mapped to a bus of a
    different width.

Instead of adding a new driver for these controllers, it is better to
    have coreboot report UART register width to libpayload, and have it
    adjust the offsets accordingly when accessing the UART.

BRANCH=none
    BUG=chrome-os-partner:31438
    TEST=with the rest of the patches integrated depthcharge console messages
         show up when running on the FPGA board

Change-Id: I30b742146069450941164afb04641b967a214d6d
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
    Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
    Original-Signed-off-by: Vadim Bendebury 
    Original-Reviewed-on: https://chromium-review.googlesource.com/240027
    Original-Reviewed-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/9738
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi

See http://review.coreboot.org/9738 for details.

-gerrit