Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... PS5, Line 223: register "SendVrMbxCmd" = "2"
I never found documentation on that PS4 exit issue; how did you verify this isn't required here?
I never verified that it was required in the first place. The issue seems to be made out of mystery meat.
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 37: register "SataTestMode" = "1"
huh? why is test mode on?
Because I want to test SATA? 😄
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 40: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[1]" = "0" :
drop disabled options - or enable devsleep cap if the board supports it (haven't checked the schemat […]
the latter part is exactly why I've left these here.
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 108: device pci 04.0 off end # CPU Thermal Subsystem
why off?
why on?
EC ACPI is missing, haven't done anything about it yet. I'll check if DPTF is enabled on vendor fw
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Angel Pons (Code Review)