[M] Change in coreboot[main]: intel/alderlake: Add helper functions for Power Management

[Nico Huber (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Sean Rhodes, Subrata Banik.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81638?usp=email )

Change subject: intel/alderlake: Add helper functions for Power Management
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Patch Set 4:

(5 comments)

Patchset:

PS4: 
If the UPDs didn't change, is there a way to write common code?

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/81638/comment/e3a20916_003512bb :
PS4, Line 799: };
Why are these declared separately? How should a mainboard dev know where to use them?
Should they use them?

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/81638/comment/c00b82e5_00f0dbf5 :
PS4, Line 504: default "auto"
I assume you are referring to the value in the FSP binary? That's generally
unknown because somebody could have set it differently.

https://review.coreboot.org/c/coreboot/+/81638/comment/10fb758a_d58c794b :
PS4, Line 506: 		s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm;
These usually aren't compatible, because coreboot values are off-by-1 to allow
the default opt-out.

https://review.coreboot.org/c/coreboot/+/81638/comment/a3013a28_f301341f :
PS4, Line 517: 		s_cfg->PcieRpL1Substates[index] = rp_cfg->PcieRpL1Substates;
Same here.