Change in coreboot[master]: mediatek/mt8183: set scp voltage setting

[hsin-hsiung wang (Code Review)]

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: set scp voltage setting
......................................................................

mediatek/mt8183: set scp voltage setting

Add scp initial voltage setting

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui and scp can boot up normally

Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf
Signed-off-by: Hsin-Hsiung Wang 
---
M src/soc/mediatek/mt8183/mt6358.c
1 file changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34205/1

diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c
index 53d2a43..8d2375a 100644
--- a/src/soc/mediatek/mt8183/mt6358.c
+++ b/src/soc/mediatek/mt8183/mt6358.c
@@ -501,6 +501,26 @@
    {0x13a6, 0x58, 0x7F, 0},
    /* [6:0]: RG_BUCK_VPROC12_VOSEL */
    {0x1426, 0x58, 0x7F, 0},
+
+	/* scp voltage initialization */
+	/* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */
+	{0x14A6, 0x20, 0x7F, 0},
+	/* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */
+	{0x14A6, 0x20, 0x7F, 8},
+	/* [0:0]: RG_BUCK_VCORE_SSHUB_EN */
+	{0x14A4, 0x1, 0x1, 0},
+	/* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */
+	{0x14A4, 0x0, 0x1, 1},
+	/* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */
+	{0x1BC6, 0x40, 0x7F, 0},
+	/* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */
+	{0x1BC6, 0x40, 0x7F, 8},
+	/* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */
+	{0x1BC4, 0x1, 0x1, 0},
+	/* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */
+	{0x1BC4, 0x0, 0x1, 1},
+	/* [4:4]: RG_SRCVOLTEN_LP_EN */
+	{0x134, 0x1, 0x1, 4},
 };

static struct pmic_setting lp_setting[] = {

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[hsin-hsiung wang (Code Review)]

Hello Julius Werner,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34205

to look at the new patch set (#2).

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

mediatek/mt8183: add scp voltage initialization

Add scp voltage initialization

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui and scp can boot up normally

Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf
Signed-off-by: Hsin-Hsiung Wang 
---
M src/soc/mediatek/mt8183/mt6358.c
1 file changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34205/2

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[hsin-hsiung wang (Code Review)]

hsin-hsiung wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

Patch Set 5:

This change is ready for review.

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[hsin-hsiung wang (Code Review)]

hsin-hsiung wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

Patch Set 5: Code-Review+1

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

Patch Set 5: Code-Review+1

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

Patch Set 5:

@jwerner can we get some blessing to merge this?

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

Patch Set 5:

(2 comments)

Remember you have to always resolve comments before you can merge now.

https://review.coreboot.org/c/coreboot/+/34205/5//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34205/5//COMMIT_MSG@10 
PS5, Line 10:
> Hi Paul, […]

Ack

https://review.coreboot.org/c/coreboot/+/34205/4/src/soc/mediatek/mt8183/mt6... 
File src/soc/mediatek/mt8183/mt6358.c:

https://review.coreboot.org/c/coreboot/+/34205/4/src/soc/mediatek/mt8183/mt6... 
PS4, Line 762: }
> Can you use a "static struct pmic_setting scp_setting" for this, instead? This should save a bit of  […]

Done

Change in coreboot[master]: mediatek/mt8183: add scp voltage initialization

[Julius Werner (Code Review)]

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34205 )

Change subject: mediatek/mt8183: add scp voltage initialization
......................................................................

mediatek/mt8183: add scp voltage initialization

Add scp voltage initialization.

BUG=b:135985700
BRANCH=none
Test=Boots correctly on Kukui and scp can boot up normally

Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf
Signed-off-by: Hsin-Hsiung Wang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34205
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
Reviewed-by: Hung-Te Lin 
---
M src/mainboard/google/kukui/romstage.c
M src/soc/mediatek/mt8183/include/soc/mt6358.h
M src/soc/mediatek/mt8183/mt6358.c
3 files changed, 31 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved
  hsin-hsiung wang: Looks good to me, but someone else must approve
  Yu-Ping Wu: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 1465243..a86690b 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -32,6 +32,7 @@
    /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */
    pmic_set_vsim2_cali(2700);
    mt_pll_raise_ca53_freq(1989 * MHz);
+	pmic_init_scp_voltage();
    rtc_boot();
    mt_mem_init(get_sdram_config());
    mtk_mmu_after_dram();
diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h
index 277ee9a..19ab5e1 100644
--- a/src/soc/mediatek/mt8183/include/soc/mt6358.h
+++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h
@@ -40,5 +40,6 @@
 void mt6358_init(void);
 void pmic_set_power_hold(bool enable);
 void pmic_set_vsim2_cali(unsigned int vsim2_mv);
+void pmic_init_scp_voltage(void);

#endif /* __SOC_MEDIATEK_MT6358_H__ */
diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c
index 53d2a43..fa928cb 100644
--- a/src/soc/mediatek/mt8183/mt6358.c
+++ b/src/soc/mediatek/mt8183/mt6358.c
@@ -731,11 +731,40 @@
    {0x1DA6, 0x0, 0x1, 3},
 };

+static struct pmic_setting scp_setting[] = {
+	/* scp voltage initialization */
+	/* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */
+	{0x14A6, 0x20, 0x7F, 0},
+	/* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */
+	{0x14A6, 0x20, 0x7F, 8},
+	/* [0:0]: RG_BUCK_VCORE_SSHUB_EN */
+	{0x14A4, 0x1, 0x1, 0},
+	/* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */
+	{0x14A4, 0x0, 0x1, 1},
+	/* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */
+	{0x1BC6, 0x40, 0x7F, 0},
+	/* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */
+	{0x1BC6, 0x40, 0x7F, 8},
+	/* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */
+	{0x1BC4, 0x1, 0x1, 0},
+	/* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */
+	{0x1BC4, 0x0, 0x1, 1},
+	/* [4:4]: RG_SRCVOLTEN_LP_EN */
+	{0x134, 0x1, 0x1, 4},
+};
 void pmic_set_power_hold(bool enable)
 {
    pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0);
 }

+void pmic_init_scp_voltage(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(scp_setting); i++)
+		pwrap_write_field(
+			scp_setting[i].addr, scp_setting[i].val,
+			scp_setting[i].mask, scp_setting[i].shift);
+}
+
 void pmic_set_vsim2_cali(unsigned int vsim2_mv)
 {
    u16 vsim2_reg, cali_mv;