Change in coreboot[master]: cpu/x86/{backup_default_smm,mp_init}.c: Convert to 96 characters line... - coreboot-gerrit

9 Aug 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44314 )
Change subject: cpu/x86/{backup_default_smm,mp_init}.c: Convert to 96 characters line length
......................................................................
cpu/x86/{backup_default_smm,mp_init}.c: Convert to 96 characters line length
Change-Id: I8ba63f6fd032bc234766cce2fe4d66cb50aaf913
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr
---
M src/cpu/x86/backup_default_smm.c
M src/cpu/x86/mp_init.c
2 files changed, 73 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44314/1

diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c
index 1672e0b..080d993 100644
--- a/src/cpu/x86/backup_default_smm.c
+++ b/src/cpu/x86/backup_default_smm.c
@@ -15,9 +15,8 @@
    	return NULL;
/*
-	 * The buffer needs to be preallocated regardless. In the non-resume
-	 * path it will be allocated for handling resume. Note that cbmem_add()
-	 * does a find before the addition.
+	 * The buffer needs to be preallocated regardless. In the non-resume path it will be
+	 * allocated for handling resume. Note that cbmem_add() does a find before the addition.
     */
    save_area = cbmem_add(CBMEM_ID_SMM_SAVE_SPACE, SMM_DEFAULT_SIZE);
@@ -33,8 +32,7 @@
    }
/*
-	 * Not the S3 resume path. No need to restore memory contents after
-	 * SMM relocation.
+	 * Not the S3 resume path. No need to restore memory contents after SMM relocation.
     */
    return NULL;
 }
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index caed8f4..1c2e641 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -39,17 +39,15 @@
 static char processor_name[49];
/*
- * A mp_flight_record details a sequence of calls for the APs to perform
- * along with the BSP to coordinate sequencing. Each flight record either
- * provides a barrier for each AP before calling the callback or the APs
- * are allowed to perform the callback without waiting. Regardless, each
- * record has the cpus_entered field incremented for each record. When
- * the BSP observes that the cpus_entered matches the number of APs
- * the bsp_call is called with bsp_arg and upon returning releases the
- * barrier allowing the APs to make further progress.
+ * A mp_flight_record details a sequence of calls for the APs to perform along with the BSP to
+ * coordinate sequencing. Each flight record either provides a barrier for each AP before
+ * calling the callback or the APs are allowed to perform the callback without waiting.
+ * Regardless, each record has the cpus_entered field incremented for each record. When the BSP
+ * observes that the cpus_entered matches the number of APs the bsp_call is called with bsp_arg
+ * and upon returning releases the barrier allowing the APs to make further progress.
  *
- * Note that ap_call() and bsp_call() can be NULL. In the NULL case the
- * callback will just not be called.
+ * Note that ap_call() and bsp_call() can be NULL. In the NULL case the callback will just not
+ * be called.
  */
 struct mp_flight_record {
    atomic_t barrier;
@@ -72,8 +70,7 @@
 #define MP_FR_NOBLOCK_APS(ap_func_, bsp_func_) \
    _MP_FLIGHT_RECORD(1, ap_func_, bsp_func_)
-/* The mp_params structure provides the arguments to the mp subsystem
- * for bringing up APs. */
+/* The mp_params structure provides the arguments to the mp subsystem for bringing up APs. */
 struct mp_params {
    int num_cpus; /* Total cpus include BSP */
    int parallel_microcode_load;
@@ -110,9 +107,9 @@
 /* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */
 extern char _binary_sipi_vector_start[];
-/* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the
- * memory range is already reserved so the OS cannot use it. That region is
- * free to use for AP bringup before SMM is initialized. */
+/* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the memory range is
+ * already reserved so the OS cannot use it. That region is free to use for AP bringup before
+ * SMM is initialized. */
 static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE;
 static const int sipi_vector_location_size = SMM_DEFAULT_SIZE;
@@ -141,8 +138,7 @@
 }
/* Returns 1 if timeout waiting for APs. 0 if target aps found. */
-static int wait_for_aps(atomic_t *val, int target, int total_delay,
-			int delay_step)
+static int wait_for_aps(atomic_t *val, int target, int total_delay, int delay_step)
 {
    int timeout = 0;
    int delayed = 0;
@@ -178,8 +174,7 @@
    stop_this_cpu();
 }
-/* By the time APs call ap_init() caching has been setup, and microcode has
- * been loaded. */
+/* By the time APs call ap_init() caching has been setup, and microcode has been loaded. */
 static void asmlinkage ap_init(unsigned int cpu)
 {
    struct cpu_info *info;
@@ -197,8 +192,7 @@
    /* Fix up APIC id with reality. */
    info->cpu->path.apic.apic_id = lapicid();
-	printk(BIOS_INFO, "AP: slot %d apic_id %x.\n", cpu,
-		info->cpu->path.apic.apic_id);
+	printk(BIOS_INFO, "AP: slot %d apic_id %x.\n", cpu, info->cpu->path.apic.apic_id);
/* Walk the flight plan */
    ap_do_flight_plan();
@@ -313,8 +307,8 @@
    module_size = ALIGN_UP(module_size, 4);
if (module_size > loc_size) {
-		printk(BIOS_CRIT, "SIPI module size (%d) > region size (%d).\n",
-		       module_size, loc_size);
+		printk(BIOS_CRIT, "SIPI module size (%d) > region size (%d).\n", module_size,
+		       loc_size);
    	return ap_count;
    }
@@ -363,8 +357,8 @@
max_cpus = p->num_cpus;
    if (max_cpus > CONFIG_MAX_CPUS) {
-		printk(BIOS_CRIT, "CPU count(%d) exceeds CONFIG_MAX_CPUS(%d)\n",
-		       max_cpus, CONFIG_MAX_CPUS);
+		printk(BIOS_CRIT, "CPU count(%d) exceeds CONFIG_MAX_CPUS(%d)\n", max_cpus,
+		       CONFIG_MAX_CPUS);
    	max_cpus = CONFIG_MAX_CPUS;
    }
@@ -376,8 +370,8 @@
    	/* Build the CPU device path */
    	cpu_path.type = DEVICE_PATH_APIC;
-		/* Assuming linear APIC space allocation. AP will set its own
-		   APIC id in the ap_init() path above. */
+		/* Assuming linear APIC space allocation. AP will set its own APIC id in the
+		 * ap_init() path above. */
    	cpu_path.apic.apic_id = info->cpu->path.apic.apic_id + i;
/* Allocate the new CPU device structure */
@@ -425,8 +419,7 @@
    sipi_vector = sipi_vector_location >> 12;
if (sipi_vector > max_vector_loc) {
-		printk(BIOS_CRIT, "SIPI vector too large! 0x%08x\n",
-		       sipi_vector);
+		printk(BIOS_CRIT, "SIPI vector too large! 0x%08x\n", sipi_vector);
    	return -1;
    }
@@ -443,8 +436,7 @@
/* Send INIT IPI to all but self. */
    lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
-	lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
-			   LAPIC_DM_INIT);
+	lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
    printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
    mdelay(10);
@@ -459,8 +451,8 @@
    }
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
-	lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
-			   LAPIC_DM_STARTUP | sipi_vector);
+	lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP |
+			   sipi_vector);
    printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete...");
    if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
    	printk(BIOS_DEBUG, "timed out.\n");
@@ -510,9 +502,8 @@
    int ret = 0;
    /*
     * Set time out for flight plan to a huge minimum value (>=1 second).
-	 * CPUs with many APs may take longer if there is contention for
-	 * resources such as UART, so scale the time out up by increments of
-	 * 100ms if needed.
+	 * CPUs with many APs may take longer if there is contention for resources such as UART,
+	 * so scale the time out up by increments of 100ms if needed.
     */
    const int timeout_us = MAX(1000000, 100000 * mp_params->num_cpus);
    const int step_us = 100;
@@ -527,8 +518,7 @@
    	/* Wait for APs if the record is not released. */
    	if (atomic_read(&rec->barrier) == 0) {
    		/* Wait for the APs to check in. */
-			if (wait_for_aps(&rec->cpus_entered, num_aps,
-					 timeout_us, step_us)) {
+			if (wait_for_aps(&rec->cpus_entered, num_aps, timeout_us, step_us)) {
    			printk(BIOS_ERR, "MP record %d timeout.\n", i);
    			ret = -1;
    		}
@@ -540,8 +530,7 @@
    	release_barrier(&rec->barrier);
    }
-	printk(BIOS_INFO, "%s done after %ld msecs.\n", __func__,
-	       stopwatch_duration_msecs(&sw));
+	printk(BIOS_INFO, "%s done after %ld msecs.\n", __func__, stopwatch_duration_msecs(&sw));
    return ret;
 }
@@ -574,21 +563,20 @@
 }
/*
- * mp_init() will set up the SIPI vector and bring up the APs according to
- * mp_params. Each flight record will be executed according to the plan. Note
- * that the MP infrastructure uses SMM default area without saving it. It's
- * up to the chipset or mainboard to either e820 reserve this area or save this
- * region prior to calling mp_init() and restoring it after mp_init returns.
+ * mp_init() will set up the SIPI vector and bring up the APs according to mp_params. Each
+ * flight record will be executed according to the plan. Note that the MP infrastructure uses
+ * SMM default area without saving it. It's up to the chipset or mainboard to either e820
+ * reserve this area or save this region prior to calling mp_init() and restoring it after
+ * mp_init returns.
  *
- * At the time mp_init() is called the MTRR MSRs are mirrored into APs then
- * caching is enabled before running the flight plan.
+ * At the time mp_init() is called the MTRR MSRs are mirrored into APs then caching is enabled
+ * before running the flight plan.
  *
  * The MP initialization has the following properties:
  * 1. APs are brought up in parallel.
  * 2. The ordering of coreboot CPU number and APIC ids is not deterministic.
- *    Therefore, one cannot rely on this property or the order of devices in
- *    the device tree unless the chipset or mainboard know the APIC ids
- *    a priori.
+ *    Therefore, one cannot rely on this property or the order of devices in the device tree
+ *    unless the chipset or mainboard know the APIC ids a priori.
  *
  * mp_init() returns < 0 on error, 0 on success.
  */
@@ -608,8 +596,7 @@
    num_cpus = allocate_cpu_devices(cpu_bus, p);
if (num_cpus < p->num_cpus) {
-		printk(BIOS_CRIT,
-		       "ERROR: More cpus requested (%d) than supported (%d).\n",
+		printk(BIOS_CRIT, "ERROR: More cpus requested (%d) than supported (%d).\n",
    	       p->num_cpus, num_cpus);
    	return -1;
    }
@@ -623,16 +610,16 @@
    if (ap_count == NULL)
    	return -1;
-	/* Make sure SIPI data hits RAM so the APs that come up will see
-	 * the startup code even if the caches are disabled.  */
+	/* Make sure SIPI data hits RAM so the APs that come up will see the startup code even
+	 * if the caches are disabled.  */
    wbinvd();
/* Start the APs providing number of APs and the cpus_entered field. */
    global_num_aps = p->num_cpus - 1;
    if (start_aps(cpu_bus, global_num_aps, ap_count) < 0) {
    	mdelay(1000);
-		printk(BIOS_DEBUG, "%d/%d eventually checked in?\n",
-		       atomic_read(ap_count), global_num_aps);
+		printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", atomic_read(ap_count),
+		       global_num_aps);
    	return -1;
    }
@@ -722,9 +709,9 @@
    }
/*
-	 * The permanent handler runs with all cpus concurrently. Precalculate
-	 * the location of the new SMBASE. If using SMM modules then this
-	 * calculation needs to match that of the module loader.
+	 * The permanent handler runs with all cpus concurrently. Precalculate the location of
+	 * the new SMBASE. If using SMM modules then this calculation needs to match that of the
+	 * module loader.
     */
    perm_smbase = mp_state.perm_smbase;
    perm_smbase -= cpu * runtime->save_state_size;
@@ -737,13 +724,10 @@
    if (CONFIG(STM)) {
    	uintptr_t mseg;
-		mseg = mp_state.perm_smbase +
-			(mp_state.perm_smsize - CONFIG_MSEG_SIZE);
+		mseg = mp_state.perm_smbase + (mp_state.perm_smsize - CONFIG_MSEG_SIZE);
-		stm_setup(mseg, p->cpu,
-				perm_smbase,
-				mp_state.perm_smbase,
-				runtime->start32_offset);
+		stm_setup(mseg, p->cpu, perm_smbase, mp_state.perm_smbase,
+			  runtime->start32_offset);
    }
 }
@@ -778,11 +762,11 @@
    return 0;
 }
-static int install_permanent_handler(int num_cpus, uintptr_t smbase,
-					size_t smsize, size_t save_state_size)
+static int install_permanent_handler(int num_cpus, uintptr_t smbase, size_t smsize,
+				     size_t save_state_size)
 {
-	/* There are num_cpus concurrent stacks and num_cpus concurrent save
-	 * state areas. Lastly, set the stack size to 1KiB. */
+	/* There are num_cpus concurrent stacks and num_cpus concurrent save state areas.
+	 * Lastly, set the stack size to 1KiB. */
    struct smm_loader_params smm_params = {
    	.per_cpu_stack_size = CONFIG_SMM_MODULE_STACK_SIZE,
    	.num_concurrent_stacks = num_cpus,
@@ -830,8 +814,8 @@
    wbinvd();
/*
-	 * Indicate that the SMM handlers have been loaded and MP
-	 * initialization is about to start.
+	 * Indicate that the SMM handlers have been loaded and MP initialization is about to
+	 * start.
     */
    if (is_smm_enabled() && mp_state.ops.pre_mp_smm_init != NULL)
    	mp_state.ops.pre_mp_smm_init();
@@ -950,19 +934,20 @@
    	memcpy(&lcb, cb, sizeof(lcb));
    	mfence();
    	store_callback(per_cpu_slot, NULL);
-		if (lcb.logical_cpu_number && (cur_cpu !=
-				lcb.logical_cpu_number))
+		if (lcb.logical_cpu_number && (cur_cpu != lcb.logical_cpu_number))
    		continue;
    	else
    		lcb.func(lcb.arg);
    }
 }
-int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num,
-		long expire_us)
+int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num, long expire_us)
 {
-	struct mp_callback lcb = { .func = func, .arg = arg,
-				.logical_cpu_number = logical_cpu_num};
+	struct mp_callback lcb = {
+		.func = func,
+		.arg = arg,
+		.logical_cpu_number = logical_cpu_num
+	};
    return run_ap_work(&lcb, expire_us);
 }
@@ -983,17 +968,14 @@
stopwatch_init(&sw);
-	ret = mp_run_on_aps(park_this_cpu, NULL, MP_RUN_ON_ALL_CPUS,
-				1000 * USECS_PER_MSEC);
+	ret = mp_run_on_aps(park_this_cpu, NULL, MP_RUN_ON_ALL_CPUS, 1000 * USECS_PER_MSEC);
duration_msecs = stopwatch_duration_msecs(&sw);
if (!ret)
-		printk(BIOS_DEBUG, "%s done after %ld msecs.\n", __func__,
-		       duration_msecs);
+		printk(BIOS_DEBUG, "%s done after %ld msecs.\n", __func__, duration_msecs);
    else
-		printk(BIOS_ERR, "%s failed after %ld msecs.\n", __func__,
-		       duration_msecs);
+		printk(BIOS_ERR, "%s failed after %ld msecs.\n", __func__, duration_msecs);
return ret;
 }
@@ -1012,8 +994,7 @@
 static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
 {
    /*
-	 * Make copy of the ops so that defaults can be set in the non-const
-	 * structure if needed.
+	 * Make copy of the ops so that defaults can be set in the non-const structure if needed.
     */
    memcpy(&state->ops, ops, sizeof(*ops));
@@ -1033,11 +1014,9 @@
    }
/*
-	 * Default to smm_initiate_relocation() if trigger callback isn't
-	 * provided.
+	 * Default to smm_initiate_relocation() if trigger callback isn't provided.
     */
-	if (CONFIG(HAVE_SMI_HANDLER) &&
-		ops->per_cpu_smm_trigger == NULL)
+	if (CONFIG(HAVE_SMI_HANDLER) && ops->per_cpu_smm_trigger == NULL)
    	mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation;
 }
@@ -1061,7 +1040,7 @@
/* Sanity check SMM state. */
    if (mp_state.perm_smsize != 0 && mp_state.smm_save_state_size != 0 &&
-		mp_state.ops.relocation_handler != NULL)
+	    mp_state.ops.relocation_handler != NULL)
    	smm_enable();
if (is_smm_enabled())
@@ -1071,7 +1050,7 @@
    /* Gather microcode information. */
    if (mp_state.ops.get_microcode_info != NULL)
    	mp_state.ops.get_microcode_info(&mp_params.microcode_pointer,
-			&mp_params.parallel_microcode_load);
+						&mp_params.parallel_microcode_load);
    mp_params.flight_plan = &mp_steps[0];
    mp_params.num_records = ARRAY_SIZE(mp_steps);
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8ba63f6fd032bc234766cce2fe4d66cb50aaf913
Gerrit-Change-Number: 44314
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr
Gerrit-MessageType: newchange



    