Change in coreboot[master]: soc/intel/alderlake: mb/intel/sm: Add tcss code - coreboot-gerrit

17 May 2021


      Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, Deepti Deshatty.
Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54089 )
Change subject: soc/intel/alderlake: mb/intel/sm: Add tcss code
......................................................................
Set Ready For Review
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/54089
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36
Gerrit-Change-Number: 54089
Gerrit-PatchSet: 2
Gerrit-Owner: Deepti Deshatty deepti.deshatty@intel.com
Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Attention: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Attention: Patrick Rudolph siro@das-labor.org
Gerrit-Attention: Deepti Deshatty deepti.deshatty@intel.com
Gerrit-Comment-Date: Mon, 17 May 2021 10:59:05 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment