Change in coreboot[master]: sb/amd/*/hudson: Use CF9 reset

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29057

Change subject: sb/amd/*/hudson: Use CF9 reset
......................................................................

sb/amd/*/hudson: Use CF9 reset

Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2
Signed-off-by: Nico Huber 
---
M src/southbridge/amd/agesa/hudson/Kconfig
M src/southbridge/amd/agesa/hudson/reset.c
M src/southbridge/amd/pi/hudson/Kconfig
M src/southbridge/amd/pi/hudson/reset.c
4 files changed, 18 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29057/1

diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 91ebe03..4f769fb 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -15,24 +15,22 @@

config SOUTHBRIDGE_AMD_AGESA_BOLTON
    bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET

config SOUTHBRIDGE_AMD_AGESA_HUDSON
    bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET

config SOUTHBRIDGE_AMD_AGESA_YANGTZE
    bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET

if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE

+config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select IOAPIC
+	select HAVE_USBDEBUG_OPTIONS
+	select HAVE_CF9_RESET
+	select HAVE_CF9_RESET_PREPARE
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
    string
    default "southbridge/amd/agesa/hudson/bootblock.c"
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 315456d..7f61c83 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -17,26 +17,17 @@
 #define __SIMPLE_DEVICE__

#include <arch/io.h>
-#include <reset.h>
+#include <cf9_reset.h>

#define HT_INIT_CONTROL     0x6c
 #define HTIC_ColdR_Detect  (1<<4)
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)

-static void set_bios_reset(void)
+void cf9_reset_prepare(void)
 {
    u32 htic;
    htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
    htic &= ~HTIC_BIOSR_Detect;
    pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
 }
-
-void do_hard_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index 5ac876f..9d803be 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -15,27 +15,25 @@

config SOUTHBRIDGE_AMD_PI_BOLTON
    bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET

config SOUTHBRIDGE_AMD_PI_AVALON
    bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET

config SOUTHBRIDGE_AMD_PI_KERN
    bool
-	select IOAPIC
-	select HAVE_USBDEBUG_OPTIONS
-	select HAVE_HARD_RESET

config HUDSON_DISABLE_IMC
    bool

if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN

+config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select IOAPIC
+	select HAVE_USBDEBUG_OPTIONS
+	select HAVE_CF9_RESET
+	select HAVE_CF9_RESET_PREPARE
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
    string
    default "southbridge/amd/pi/hudson/bootblock.c"
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index f80e2d4..7f61c83 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -17,27 +17,17 @@
 #define __SIMPLE_DEVICE__

#include <arch/io.h>
-#include <reset.h>
+#include <cf9_reset.h>

#define HT_INIT_CONTROL     0x6c
 #define HTIC_ColdR_Detect  (1<<4)
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)

-static void set_bios_reset(void)
+void cf9_reset_prepare(void)
 {
    u32 htic;
    htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
    htic &= ~HTIC_BIOSR_Detect;
    pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
 }
-
-
-void do_hard_reset(void)
-{
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
-	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
-	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}