Attention is currently required from: Felix Singer, Nico Huber, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52789 )
Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/skylake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/52789/comment/e243d712_4e70dd5f
PS5, Line 120: 0x4c4
That's an interesting thought. My understanding was that with the _ADR
above this "Device" would only be treated as present if it matches an
enumerated PCI device in the OS.
My understanding matches what you outlined here. However, I think the device will be enumerated in the OS unless it is power and clock gated before jumping into OS. This is where `ScsSdCardEnabled` seems to play a role. If the mainboard has initialized devicetree correctly to mark SD controller as `off`, then it should be power and clock gated by FSP, thus preventing it from showing up on the PCI bus.
Would the OS try to switch power states of a PCI device that it can't see?
My understanding is that if the OS doesn't see the device, then it won't really switch the power states for the device.
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