Change in coreboot[master]: soc/intel/jsl: Add CdClock config

[Angel Pons (Code Review)]

Attention is currently required from: Jamie Chen, Henry Sun, Tim Wawrzynczak, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jsl: Add CdClock config
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Patch Set 16: Code-Review+1

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60009/comment/33731f0f_b84f7e8c 
PS16, Line 7: CdClock
nit: `CdClock frequency`

https://review.coreboot.org/c/coreboot/+/60009/comment/811022c0_1fc010c3 
PS16, Line 9: This dev tree config controls the CdClock for Jasper Lake.
I'd reword and expand this a bit, stating what `CdClock` means and removing the redundant `for Jasper Lake` part (already in the summary as `soc/intel/jsl`):

Add a devicetree setting to configure the CdClock (Core Display Clock)
 frequency through a FSP UPD. Because the value for this UPD's default
 setting is non-zero and devicetree settings default to 0 if not set,
 adapt the devicetree values so that the value for the UPD's default
 setting is used when the devicetree setting is zero.

Patchset:

PS16: 
After addressing my comments, LGTM.