Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files ......................................................................
Merge Haswell and Broadwell files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same.
Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c D src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell_init.c D src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/haswell/acpi.c A src/cpu/intel/haswell/acpi_common.c M src/cpu/intel/haswell/bootblock.c A src/cpu/intel/haswell/cstate_def.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c A src/cpu/intel/haswell/hsw_bdw_init_common.c M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/broadwell/Makefile.inc M src/northbridge/intel/broadwell/acpi/broadwell.asl D src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/igd.c D src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c R src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c A src/northbridge/intel/haswell/northbridge_common.c M src/northbridge/intel/haswell/report_platform.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/spi.h 36 files changed, 1,129 insertions(+), 2,636 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/1
diff --git a/src/cpu/intel/broadwell/Makefile.inc b/src/cpu/intel/broadwell/Makefile.inc index ad5dc5b..4b89975 100644 --- a/src/cpu/intel/broadwell/Makefile.inc +++ b/src/cpu/intel/broadwell/Makefile.inc @@ -6,7 +6,7 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common
-bootblock-y += bootblock.c +bootblock-y += ../haswell/bootblock.c bootblock-y += ../../../cpu/intel/car/bootblock.c bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S @@ -25,7 +25,7 @@
romstage-y += romstage.c
-ramstage-y += smmrelocate.c +ramstage-y += ../haswell/smmrelocate.c
bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c diff --git a/src/cpu/intel/broadwell/acpi.c b/src/cpu/intel/broadwell/acpi.c index a63914c..f96c260 100644 --- a/src/cpu/intel/broadwell/acpi.c +++ b/src/cpu/intel/broadwell/acpi.c @@ -25,99 +25,8 @@ #include <southbridge/intel/wildcatpoint/soc_chip.h> #include <intelblocks/cpulib.h>
-/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/cstate_def.c>
static int cstate_set_s0ix[3] = { C_STATE_C1E, @@ -131,22 +40,6 @@ C_STATE_C7S_LONG_LAT };
-static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - static void generate_C_state_entries(void) { acpi_cstate_t map[3]; @@ -169,229 +62,13 @@ acpigen_write_CST_package(map, ARRAY_SIZE(map)); }
-static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) +static inline void get_pmbase(void) { - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); + return ACPI_BASE_ADDRESS; }
-static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CPU_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor _SB.CPUx */ - acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID - 1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID - 1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/acpi_common.c>
unsigned long acpi_madt_irq_overrides(unsigned long current) { diff --git a/src/cpu/intel/broadwell/bootblock.c b/src/cpu/intel/broadwell/bootblock.c deleted file mode 100644 index 72f8205..0000000 --- a/src/cpu/intel/broadwell/bootblock.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/bootblock.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <halt.h> -#include <southbridge/intel/wildcatpoint/rcba.h> -#include <delay.h> - -#include <cpu/intel/broadwell/broadwell.h> - -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u32 soft_reset; - u8 nominal_ratio; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set flex ratio in soft reset data register bits 11:6. - * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); - soft_reset &= ~(0x3f << 6); - soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; - - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); - - /* Delay before reset to avoid potential TPM lockout */ - mdelay(30); - - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); -} - -void bootblock_early_cpu_init(void) -{ - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); -} diff --git a/src/cpu/intel/broadwell/broadwell_init.c b/src/cpu/intel/broadwell/broadwell_init.c index 5d26232..7c0ce54 100644 --- a/src/cpu/intel/broadwell/broadwell_init.c +++ b/src/cpu/intel/broadwell/broadwell_init.c @@ -36,80 +36,12 @@
/** haswell_is_ult **/
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly - * when a core is woken up. */ -static int pcode_ready(void) -{ - int wait_count; - const int delay_step = 10; +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/hsw_bdw_init_common.c>
- wait_count = 0; - do { - if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) - return 0; - wait_count += delay_step; - udelay(delay_step); - } while (wait_count < 1000); +/** cpu_config_tdp_levels **/
- return -1; -} - -static void calibrate_24mhz_bclk(void) -{ - int err_code; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return; - } - - /* A non-zero value initiates the PCODE calibration. */ - MCHBAR32(BIOS_MAILBOX_DATA) = ~0; - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return; - } - - err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", - err_code); - - /* Read the calibrated value. */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); - return; - } - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); -} - -static u32 pcode_mailbox_read(u32 command) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return 0; - } - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return 0; - } - - /* Read mailbox */ - return MCHBAR32(BIOS_MAILBOX_DATA); -} +/** set_power_limits **/
static int pcode_mailbox_write(u32 command, u32 data) { @@ -195,56 +127,6 @@ pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); }
-static void configure_pch_power_sharing(void) -{ - u32 pch_power, pch_power_ext, pmsync, pmsync2; - int i; - - /* Read PCH Power levels from PCODE */ - pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); - pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); - - printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); - - pmsync = RCBA32(PMSYNC_CONFIG); - pmsync2 = RCBA32(PMSYNC_CONFIG2); - - /* Program PMSYNC_TPR_CONFIG PCH power limit values - * pmsync[0:4] = mailbox[0:5] - * pmsync[8:12] = mailbox[6:11] - * pmsync[16:20] = mailbox[12:17] - */ - for (i = 0; i < 3; i++) { - u32 level = pch_power & 0x3f; - pch_power >>= 6; - pmsync &= ~(0x1f << (i * 8)); - pmsync |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG) = pmsync; - - /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values - * pmsync2[0:4] = mailbox[23:18] - * pmsync2[8:12] = mailbox_ext[6:11] - * pmsync2[16:20] = mailbox_ext[12:17] - * pmsync2[24:28] = mailbox_ext[18:22] - */ - pmsync2 &= ~0x1f; - pmsync2 |= pch_power & 0x1f; - - for (i = 1; i < 4; i++) { - u32 level = pch_power_ext & 0x3f; - pch_power_ext >>= 6; - pmsync2 &= ~(0x1f << (i * 8)); - pmsync2 |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG2) = pmsync2; -} - -/** cpu_config_tdp_levels **/ - -/** set_power_limits **/ - static void configure_c_states(void) { msr_t msr; @@ -321,50 +203,6 @@ } }
-static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -} - -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -409,22 +247,6 @@ printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); }
-static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - /* All CPUs including BSP will run the following function. */ static void cpu_core_init(struct device *cpu) { @@ -457,9 +279,6 @@ enable_turbo(); }
-/* MP initialization support. */ -static const void *microcode_patch; - static void pre_mp_init(void) { /* Setup MTRRs based on physical address size. */ @@ -471,37 +290,6 @@ configure_pch_power_sharing(); }
-static int get_cpu_count(void) -{ - msr_t msr; - int num_threads; - int num_cores; - - msr = rdmsr(MSR_CORE_THREAD_COUNT); - num_threads = (msr.lo >> 0) & 0xffff; - num_cores = (msr.lo >> 16) & 0xffff; - printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); - - return num_threads; -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; - *parallel = 1; -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - static void post_mp_init(void) { /* Set Max Ratio */ diff --git a/src/cpu/intel/broadwell/smmrelocate.c b/src/cpu/intel/broadwell/smmrelocate.c deleted file mode 100644 index 5599c0b..0000000 --- a/src/cpu/intel/broadwell/smmrelocate.c +++ /dev/null @@ -1,265 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> -#include <cpu/intel/smm_reloc.h> -#include <console/console.h> -#include <northbridge/intel/broadwell/broadwell.h> -#include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <smp/node.h> -#include "broadwell.h" - - -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) -{ - u32 smbase; - u32 iedbase; - - /* The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ - smbase = staggered_smbase; - iedbase = relo_params->ied_base; - - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); - - /* All threads need to set IEDBASE and SMBASE to the relocated - * handler region. However, the save state location depends on the - * smm_save_state_in_msrs field in the relocation parameters. If - * smm_save_state_in_msrs is non-zero then the CPUs are relocating - * the SMM handler in parallel, and each CPUs save state area is - * located in their respective MSR space. If smm_save_state_in_msrs - * is zero then the SMM relocation is happening serially so the - * save state is at the same default location for all CPUs. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smbase_msr; - msr_t iedbase_msr; - - smbase_msr.lo = smbase; - smbase_msr.hi = 0; - - /* According the BWG the IEDBASE MSR is in bits 63:32. It's - * not clear why it differs from the SMBASE MSR. */ - iedbase_msr.lo = 0; - iedbase_msr.hi = iedbase; - - wrmsr(SMBASE_MSR, smbase_msr); - wrmsr(IEDBASE_MSR, iedbase_msr); - } else { - em64t101_smm_state_save_area_t *save_state; - - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); - - save_state->smbase = smbase; - save_state->iedbase = iedbase; - } -} - -/* Returns 1 if SMM MSR save state was set. */ -static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params) -{ - msr_t smm_mca_cap; - - smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); - if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.hi = 0; - smm_feature_control.lo |= SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - relo_params->smm_save_state_in_msrs = 1; - } - return relo_params->smm_save_state_in_msrs; -} - -/* The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) -{ - msr_t mtrr_cap; - struct smm_relocation_params *relo_params = &smm_reloc_params; - - printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); - - /* Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. */ - if (cpu == 0) { - /* If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. */ - if (relo_params->smm_save_state_in_msrs) { - msr_t smm_feature_control; - - smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR); - smm_feature_control.lo &= ~SMM_CPU_SAVE_EN; - wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); - } else if (bsp_setup_msr_save_state(relo_params)) - /* Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. */ - return; - } - - /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); - - /* Write PRMRR and SMRR MSRs based on indicated support. */ - mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) - write_smrr(relo_params); - - if (mtrr_cap.lo & PRMRR_SUPPORTED) { - write_prmrr(relo_params); - /* UNCORE_PRMRR msrs are package level. Therefore, only - * configure these MSRs on the BSP. */ - if (cpu == 0) - write_uncore_prmrr(relo_params); - } -} - -static void fill_in_relocation_params(struct smm_relocation_params *params) -{ - uintptr_t tseg_base; - size_t tseg_size; - - u32 prmrr_base; - u32 prmrr_size; - int phys_bits; - /* All range registers are aligned to 4KiB */ - const u32 rmask = ~((1 << 12) - 1); - - /* Some of the range registers are dependent on the number of physical - * address bits supported. */ - phys_bits = cpuid_eax(0x80000008) & 0xff; - - /* The range bounded by the TSEGMB and BGSM registers encompasses the - * SMRAM range as well as the IED range. However, the SMRAM available - * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. - */ - smm_region(&tseg_base, &tseg_size); - - /* SMRR has 32-bits of valid address aligned to 4KiB. */ - params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK; - params->smrr_base.hi = 0; - params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID; - params->smrr_mask.hi = 0; - - smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); - - /* The PRMRR and UNCORE_PRMRR are at IEDBASE + 2MiB */ - prmrr_base = (params->ied_base + (2 << 20)) & rmask; - prmrr_size = params->ied_size - (2 << 20); - - /* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent - * on the number of physical address bits supported. */ - params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK; - params->prmrr_base.hi = 0; - params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask) - | MTRR_PHYS_MASK_VALID; - params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1; - - /* UNCORE_PRMRR has 39 bits of valid address aligned to 4KiB. */ - params->uncore_prmrr_base.lo = prmrr_base; - params->uncore_prmrr_base.hi = 0; - params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; - params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; -} - -static void setup_ied_area(struct smm_relocation_params *params) -{ - char *ied_base; - - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = params->ied_size, - .reserved = {0}, - }; - - ied_base = (void *)params->ied_base; - - /* Place IED header at IEDBASE. */ - memcpy(ied_base, &ied, sizeof(ied)); - - /* Zero out 32KiB at IEDBASE + 1MiB */ - memset(ied_base + (1 << 20), 0, (32 << 10)); -} - -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) -{ - printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - - fill_in_relocation_params(&smm_reloc_params); - - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - - setup_ied_area(&smm_reloc_params); - - *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); -} - -void smm_initialize(void) -{ - /* Clear the SMM state in the southbridge. */ - smm_southbridge_clear_state(); - - /* - * Run the relocation handler for on the BSP to check and set up - * parallel SMM relocation. - */ - smm_initiate_relocation(); - - if (smm_reloc_params.smm_save_state_in_msrs) - printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); -} - -/* The default SMM entry can happen in parallel or serially. If the - * default SMM entry is done in parallel the BSP has already setup - * the saving state to each CPU's MSRs. At least one save state size - * is required for the initial SMM entry for the BSP to determine if - * parallel SMM relocation is even feasible. */ -void smm_relocate(void) -{ - /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. - */ - if (smm_reloc_params.smm_save_state_in_msrs) - smm_initiate_relocation_parallel(); - else if (!boot_cpu()) - smm_initiate_relocation(); -} - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_path_on_root(SA_DEVFN_ROOT), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 676acce..0deb358 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,22 +14,6 @@
#include <southbridge/intel/lynxpoint/pch.h>
-static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - static void generate_cstate_entries(acpi_cstate_t *cstates, int c1, int c2, int c3) { @@ -109,229 +93,8 @@ acpigen_pop_len(); }
-static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * HASWELL_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * HASWELL_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor _SB.CPUx */ - acpigen_write_processor( - (cpuID-1)*cores_per_package+coreID-1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID-1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID-1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/acpi_common.c>
struct chip_operations cpu_intel_haswell_ops = { CHIP_NAME("Intel Haswell CPU") diff --git a/src/cpu/intel/haswell/acpi_common.c b/src/cpu/intel/haswell/acpi_common.c new file mode 100644 index 0000000..545f319 --- /dev/null +++ b/src/cpu/intel/haswell/acpi_common.c @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static acpi_tstate_t tss_table_fine[] = { + { 100, 1000, 0, 0x00, 0 }, + { 94, 940, 0, 0x1f, 0 }, + { 88, 880, 0, 0x1e, 0 }, + { 82, 820, 0, 0x1d, 0 }, + { 75, 760, 0, 0x1c, 0 }, + { 69, 700, 0, 0x1b, 0 }, + { 63, 640, 0, 0x1a, 0 }, + { 57, 580, 0, 0x19, 0 }, + { 50, 520, 0, 0x18, 0 }, + { 44, 460, 0, 0x17, 0 }, + { 38, 400, 0, 0x16, 0 }, + { 32, 340, 0, 0x15, 0 }, + { 25, 280, 0, 0x14, 0 }, + { 19, 220, 0, 0x13, 0 }, + { 13, 160, 0, 0x12, 0 }, +}; + +static acpi_tstate_t tss_table_coarse[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1f, 0 }, + { 75, 750, 0, 0x1e, 0 }, + { 63, 625, 0, 0x1d, 0 }, + { 50, 500, 0, 0x1c, 0 }, + { 38, 375, 0, 0x1b, 0 }, + { 25, 250, 0, 0x1a, 0 }, + { 13, 125, 0, 0x19, 0 }, +}; + +static void generate_T_state_entries(int core, int cores_per_package) +{ + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set a T-state limit that can be modified in NVS */ + acpigen_write_TPC("\TLVL"); + + /* + * CPUID.(EAX=6):EAX[5] indicates support + * for extended throttle levels. + */ + if (cpuid_eax(6) & (1 << 5)) + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_fine), tss_table_fine); + else + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_coarse), tss_table_coarse); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +#ifndef HASWELL_BCLK +#define HASWELL_BCLK CPU_BCLK +#endif + +static void generate_P_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * HASWELL_BCLK; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > PSS_MAX_ENTRIES-1) { + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_turbo << 8, /*control*/ + ratio_turbo << 8); /*status*/ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_max << 8, /*control*/ + ratio_max << 8); /*status*/ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * HASWELL_BCLK; + + acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio << 8, /*control*/ + ratio << 8); /*status*/ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +void generate_cpu_entries(const struct device *device) +{ + int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpuID = 1; cpuID <= numcpus; cpuID++) { + for (coreID = 1; coreID <= cores_per_package; coreID++) { + if (coreID > 1) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor _SB.CPUx */ + acpigen_write_processor( + (cpuID - 1) * cores_per_package+coreID - 1, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_P_state_entries( + coreID - 1, cores_per_package); + + /* Generate C-state tables */ + generate_C_state_entries(); + + /* Generate T-state tables */ + generate_T_state_entries( + cpuID - 1, cores_per_package); + + acpigen_pop_len(); + } + } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(cores_per_package); +} diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index c9e3f2a..6b5d85f 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -5,11 +5,17 @@ #include <cpu/x86/msr.h> #include <arch/io.h> #include <halt.h> +#include <delay.h>
-#include "haswell.h" - +#if CONFIG(CPU_INTEL_HASWELL) +#include <cpu/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h>
+#elif CONFIG(CPU_INTEL_BROADWELL) +#include <cpu/intel/broadwell/broadwell.h> +#include <southbridge/intel/wildcatpoint/rcba.h> +#endif + static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -50,6 +56,10 @@ /* Set soft reset control to use register value */ RCBA32_OR(SOFT_RESET_CTRL, 1);
+ /* Delay before reset to avoid potential TPM lockout */ + if (CONFIG(CPU_INTEL_BROADWELL)) + mdelay(30); + /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); diff --git a/src/cpu/intel/haswell/cstate_def.c b/src/cpu/intel/haswell/cstate_def.c new file mode 100644 index 0000000..ede75b0 --- /dev/null +++ b/src/cpu/intel/haswell/cstate_def.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +/* + * List of supported C-states in this processor. Only the ULT parts support C8, + * C9, and C10. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C7S_SHORT_LAT, /* 8 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C3] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = 900, + .resource = MWAIT_RES(1, 0), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 800, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 800, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(3), + .power = 600, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(4), + .power = 500, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(5), + .power = 400, + .resource = MWAIT_RES(6, 0), + }, +}; diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7906b83..e47429c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -29,15 +29,30 @@ #define MSR_LT_LOCK_MEMORY 0x2e7
#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 - +#define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1)
#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b @@ -77,6 +92,14 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c
+/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bits */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638..e88c9ef 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -34,99 +34,8 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10))
-/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/cstate_def.c>
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -207,179 +116,9 @@ return ult; }
-/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly - * when a core is woken up. */ -static int pcode_ready(void) -{ - int wait_count; - const int delay_step = 10;
- wait_count = 0; - do { - if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) - return 0; - wait_count += delay_step; - udelay(delay_step); - } while (wait_count < 1000); - - return -1; -} - -static void calibrate_24mhz_bclk(void) -{ - int err_code; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return; - } - - /* A non-zero value initiates the PCODE calibration. */ - MCHBAR32(BIOS_MAILBOX_DATA) = ~0; - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return; - } - - err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", - err_code); - - /* Read the calibrated value. */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = - MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); - return; - } - - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); -} - -static u32 pcode_mailbox_read(u32 command) -{ - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); - return 0; - } - - /* Send command and start transaction */ - MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; - - if (pcode_ready() < 0) { - printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); - return 0; - } - - /* Read mailbox */ - return MCHBAR32(BIOS_MAILBOX_DATA); -} - -static void initialize_vr_config(void) -{ - msr_t msr; - - printk(BIOS_DEBUG, "Initializing VR config.\n"); - - /* Configure VR_CURRENT_CONFIG. */ - msr = rdmsr(MSR_VR_CURRENT_CONFIG); - /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid - * on ULT systems. */ - msr.hi &= 0xc0000000; - msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ - msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ - - if (haswell_is_ult()) - msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ - /* Leave the max instantaneous current limit (12:0) to default. */ - wrmsr(MSR_VR_CURRENT_CONFIG, msr); - - /* Configure VR_MISC_CONFIG MSR. */ - msr = rdmsr(MSR_VR_MISC_CONFIG); - /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ - msr.hi &= ~(0x3ff << (40 - 32)); - msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ - /* Set IOUT_OFFSET to 0. */ - msr.hi &= ~0xff; - /* Set exit ramp rate to fast. */ - msr.hi |= (1 << (50 - 32)); - /* Set entry ramp rate to slow. */ - msr.hi &= ~(1 << (51 - 32)); - /* Enable decay mode on C-state entry. */ - msr.hi |= (1 << (52 - 32)); - if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ - msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); - } - /* Set MIN_VID (31:24) to allow CPU to have full control. */ - msr.lo &= ~0xff000000; - wrmsr(MSR_VR_MISC_CONFIG, msr); - - /* Configure VR_MISC_CONFIG2 MSR. */ - if (haswell_is_ult()) { - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; - wrmsr(MSR_VR_MISC_CONFIG2, msr); - } -} - -static void configure_pch_power_sharing(void) -{ - u32 pch_power, pch_power_ext, pmsync, pmsync2; - int i; - - /* Read PCH Power levels from PCODE */ - pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); - pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); - - printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); - - pmsync = RCBA32(PMSYNC_CONFIG); - pmsync2 = RCBA32(PMSYNC_CONFIG2); - - /* Program PMSYNC_TPR_CONFIG PCH power limit values - * pmsync[0:4] = mailbox[0:5] - * pmsync[8:12] = mailbox[6:11] - * pmsync[16:20] = mailbox[12:17] - */ - for (i = 0; i < 3; i++) { - u32 level = pch_power & 0x3f; - pch_power >>= 6; - pmsync &= ~(0x1f << (i * 8)); - pmsync |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG) = pmsync; - - /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values - * pmsync2[0:4] = mailbox[23:18] - * pmsync2[8:12] = mailbox_ext[6:11] - * pmsync2[16:20] = mailbox_ext[12:17] - * pmsync2[24:28] = mailbox_ext[18:22] - */ - pmsync2 &= ~0x1f; - pmsync2 |= pch_power & 0x1f; - - for (i = 1; i < 4; i++) { - u32 level = pch_power_ext & 0x3f; - pch_power_ext >>= 6; - pmsync2 &= ~(0x1f << (i * 8)); - pmsync2 |= (level & 0x1f) << (i * 8); - } - RCBA32(PMSYNC_CONFIG2) = pmsync2; -} +/* FIXME: For verification purposes only */ +#include <cpu/intel/haswell/hsw_bdw_init_common.c>
int cpu_config_tdp_levels(void) { @@ -466,6 +205,59 @@ } }
+static void initialize_vr_config(void) +{ + msr_t msr; + + printk(BIOS_DEBUG, "Initializing VR config.\n"); + + /* Configure VR_CURRENT_CONFIG. */ + msr = rdmsr(MSR_VR_CURRENT_CONFIG); + /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid + * on ULT systems. */ + msr.hi &= 0xc0000000; + msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ + msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ + msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ + + if (haswell_is_ult()) + msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ + /* Leave the max instantaneous current limit (12:0) to default. */ + wrmsr(MSR_VR_CURRENT_CONFIG, msr); + + /* Configure VR_MISC_CONFIG MSR. */ + msr = rdmsr(MSR_VR_MISC_CONFIG); + /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ + msr.hi &= ~(0x3ff << (40 - 32)); + msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ + /* Set IOUT_OFFSET to 0. */ + msr.hi &= ~0xff; + /* Set exit ramp rate to fast. */ + msr.hi |= (1 << (50 - 32)); + /* Set entry ramp rate to slow. */ + msr.hi &= ~(1 << (51 - 32)); + /* Enable decay mode on C-state entry. */ + msr.hi |= (1 << (52 - 32)); + if (haswell_is_ult()) { + /* Set the slow ramp rate to be fast ramp rate / 4 */ + msr.hi &= ~(0x3 << (53 - 32)); + msr.hi |= (0x01 << (53 - 32)); + } + /* Set MIN_VID (31:24) to allow CPU to have full control. */ + msr.lo &= ~0xff000000; + wrmsr(MSR_VR_MISC_CONFIG, msr); + + /* Configure VR_MISC_CONFIG2 MSR. */ + if (haswell_is_ult()) { + msr = rdmsr(MSR_VR_MISC_CONFIG2); + msr.lo &= ~0xffff; + /* Allow CPU to control minimum voltage completely (15:8) and + * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ + msr.lo |= 0x006f; + wrmsr(MSR_VR_MISC_CONFIG2, msr); + } +} + static void configure_c_states(void) { msr_t msr; @@ -556,50 +348,6 @@ } }
-static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); - - /* Disable Thermal interrupts */ - msr.lo = 0; - msr.hi = 0; - wrmsr(IA32_THERM_INTERRUPT, msr); - - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -} - -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - -static void configure_dca_cap(void) -{ - uint32_t feature_flag; - msr_t msr; - - /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ - feature_flag = cpu_get_feature_flags_ecx(); - if (feature_flag & CPUID_DCA) { - msr = rdmsr(IA32_PLATFORM_DCA_CAP); - msr.lo |= 1; - wrmsr(IA32_PLATFORM_DCA_CAP, msr); - } -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; @@ -642,22 +390,6 @@ policy); }
-static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - /* All CPUs including BSP will run the following function. */ static void haswell_init(struct device *cpu) { @@ -693,9 +425,6 @@ enable_turbo(); }
-/* MP initialization support. */ -static const void *microcode_patch; - static void pre_mp_init(void) { /* Setup MTRRs based on physical address size. */ @@ -710,37 +439,6 @@ } }
-static int get_cpu_count(void) -{ - msr_t msr; - int num_threads; - int num_cores; - - msr = rdmsr(MSR_CORE_THREAD_COUNT); - num_threads = (msr.lo >> 0) & 0xffff; - num_cores = (msr.lo >> 16) & 0xffff; - printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); - - return num_threads; -} - -static void get_microcode_info(const void **microcode, int *parallel) -{ - microcode_patch = intel_microcode_find(); - *microcode = microcode_patch; - *parallel = 1; -} - -static void per_cpu_smm_trigger(void) -{ - /* Relocate the SMM handler. */ - smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); -} - static void post_mp_init(void) { /* Now that all APs have been relocated as well as the BSP let SMIs diff --git a/src/cpu/intel/haswell/hsw_bdw_init_common.c b/src/cpu/intel/haswell/hsw_bdw_init_common.c new file mode 100644 index 0000000..b32ccf9 --- /dev/null +++ b/src/cpu/intel/haswell/hsw_bdw_init_common.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly + * when a core is woken up. */ +static int pcode_ready(void) +{ + int wait_count; + const int delay_step = 10; + + wait_count = 0; + do { + if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) + return 0; + wait_count += delay_step; + udelay(delay_step); + } while (wait_count < 1000); + + return -1; +} + +static void calibrate_24mhz_bclk(void) +{ + int err_code; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return; + } + + /* A non-zero value initiates the PCODE calibration. */ + MCHBAR32(BIOS_MAILBOX_DATA) = ~0; + MCHBAR32(BIOS_MAILBOX_INTERFACE) = + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return; + } + + err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; + + printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + err_code); + + /* Read the calibrated value. */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = + MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); + return; + } + + printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + MCHBAR32(BIOS_MAILBOX_DATA)); +} + +static u32 pcode_mailbox_read(u32 command) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return 0; + } + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return 0; + } + + /* Read mailbox */ + return MCHBAR32(BIOS_MAILBOX_DATA); +} + +static void configure_pch_power_sharing(void) +{ + u32 pch_power, pch_power_ext, pmsync, pmsync2; + int i; + + /* Read PCH Power levels from PCODE */ + pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); + pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); + + printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", + pch_power, pch_power_ext); + + pmsync = RCBA32(PMSYNC_CONFIG); + pmsync2 = RCBA32(PMSYNC_CONFIG2); + + /* Program PMSYNC_TPR_CONFIG PCH power limit values + * pmsync[0:4] = mailbox[0:5] + * pmsync[8:12] = mailbox[6:11] + * pmsync[16:20] = mailbox[12:17] + */ + for (i = 0; i < 3; i++) { + u32 level = pch_power & 0x3f; + pch_power >>= 6; + pmsync &= ~(0x1f << (i * 8)); + pmsync |= (level & 0x1f) << (i * 8); + } + RCBA32(PMSYNC_CONFIG) = pmsync; + + /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values + * pmsync2[0:4] = mailbox[23:18] + * pmsync2[8:12] = mailbox_ext[6:11] + * pmsync2[16:20] = mailbox_ext[12:17] + * pmsync2[24:28] = mailbox_ext[18:22] + */ + pmsync2 &= ~0x1f; + pmsync2 |= pch_power & 0x1f; + + for (i = 1; i < 4; i++) { + u32 level = pch_power_ext & 0x3f; + pch_power_ext >>= 6; + pmsync2 &= ~(0x1f << (i * 8)); + pmsync2 |= (level & 0x1f) << (i * 8); + } + RCBA32(PMSYNC_CONFIG2) = pmsync2; +} + +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + uint32_t feature_flag; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + feature_flag = cpu_get_feature_flags_ecx(); + if (feature_flag & CPUID_DCA) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void configure_mca(void) +{ + msr_t msr; + int i; + int num_banks; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & 0xff; + msr.lo = msr.hi = 0; + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + for (i = 0; i < num_banks; i++) + wrmsr(IA32_MC0_STATUS + (i * 4), msr); +} + +static int get_cpu_count(void) +{ + msr_t msr; + int num_threads; + int num_cores; + + msr = rdmsr(MSR_CORE_THREAD_COUNT); + num_threads = (msr.lo >> 0) & 0xffff; + num_cores = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", + num_cores, num_threads); + + return num_threads; +} + +/* MP initialization support. */ +static const void *microcode_patch; + +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5e4e028..309c4fa 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -12,28 +12,16 @@ #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> #include <console/console.h> -#include <northbridge/intel/haswell/haswell.h> -#include <southbridge/intel/lynxpoint/pch.h> #include <smp/node.h> -#include "haswell.h"
-#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 +#if CONFIG(CPU_INTEL_HASWELL) +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h>
-#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - - +#elif CONFIG(CPU_INTEL_BROADWELL) +#include <northbridge/intel/broadwell/broadwell.h> +#include <cpu/intel/broadwell/broadwell.h> +#endif
static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -199,7 +187,7 @@ params->uncore_prmrr_base.lo = prmrr_base; params->uncore_prmrr_base.hi = 0; params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) | - MTRR_PHYS_MASK_VALID; + MTRR_PHYS_MASK_VALID; params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1; }
diff --git a/src/northbridge/intel/broadwell/Makefile.inc b/src/northbridge/intel/broadwell/Makefile.inc index 69ea826..59b200b 100644 --- a/src/northbridge/intel/broadwell/Makefile.inc +++ b/src/northbridge/intel/broadwell/Makefile.inc @@ -2,7 +2,7 @@
CPPFLAGS_common += -Isrc/northbridge/intel/broadwell/include
-bootblock-y += bootblock.c +bootblock-y += ../haswell/bootblock.c
ramstage-y += acpi.c
@@ -15,7 +15,7 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c -ramstage-y += minihd.c +ramstage-y += ../haswell/minihd.c
ramstage-y += northbridge.c
diff --git a/src/northbridge/intel/broadwell/acpi/broadwell.asl b/src/northbridge/intel/broadwell/acpi/broadwell.asl index 12296cb..2f9c071 100644 --- a/src/northbridge/intel/broadwell/acpi/broadwell.asl +++ b/src/northbridge/intel/broadwell/acpi/broadwell.asl @@ -2,170 +2,7 @@
#include <southbridge/intel/wildcatpoint/iomap.h>
-Name (_HID, EISAID ("PNP0A08")) // PCIe -Name (_CID, EISAID ("PNP0A03")) // PCI - -Name (_BBN, 0) - -Device (MCHC) -{ - Name (_ADR, 0x00000000) // 0:0.0 - - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset (0x70), // ME Base Address - MEBA, 64, - Offset (0xa0), // Top of Used Memory - TOM, 64, - Offset (0xbc), // Top of Low Used Memory - TLUD, 32, - } -} - -// Current Resource Settings -Name (MCRS, ResourceTemplate() -{ - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) -}) - -Method (_CRS, 0, Serialized) -{ - // Find PCI resource area in MCRS - CreateDwordField(MCRS, ^PM01._MIN, PMIN) - CreateDwordField(MCRS, ^PM01._MAX, PMAX) - CreateDwordField(MCRS, ^PM01._LEN, PLEN) - - // Fix up PCI memory region - // Start with Top of Lower Usable DRAM - // Lower 20 bits of TOLUD register need to be masked since they contain lock and - // reserved bits. - Local0 = ^MCHC.TLUD & (0xfff << 20) - Local1 = ^MCHC.MEBA - - // Check if ME base is equal - If (Local0 == Local1) { - // Use Top Of Memory instead - // Lower 20 bits of TOM register need to be masked since they contain lock and - // reserved bits. - Local0 = ^MCHC.TOM & (0x7ffff << 20) - } - - PMIN = Local0 - PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 - PLEN = (PMAX - PMIN) + 1 - - Return (MCRS) -} +#include <northbridge/intel/haswell/acpi/hostbridge.asl>
/* PCI Device Resource Consumption */ Device (PDRC) @@ -193,5 +30,8 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl"
-/* Configurable TDP */ -#include "ctdp.asl" +Scope (_SB.PCI0.MCHC) +{ + /* Configurable TDP */ + #include <northbridge/intel/haswell/acpi/ctdp.asl> +} diff --git a/src/northbridge/intel/broadwell/bootblock.c b/src/northbridge/intel/broadwell/bootblock.c deleted file mode 100644 index d661f57..0000000 --- a/src/northbridge/intel/broadwell/bootblock.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/bootblock.h> -#include <device/pci_ops.h> -#include <southbridge/intel/wildcatpoint/pci_devs.h> -#include <northbridge/intel/broadwell/broadwell.h> - -void bootblock_early_northbridge_init(void) -{ - uint32_t reg; - - /* - * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent - * non-explicit config accesses use MCFG. This code also assumes that - * bootblock_northbridge_init() is the first thing called in the non-asm - * boot block code. The final assumption is that no assembly code is using - * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. - * - * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. - */ - reg = 0; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); -} diff --git a/src/northbridge/intel/broadwell/broadwell.h b/src/northbridge/intel/broadwell/broadwell.h index 1a8e6cf..ed8356d 100644 --- a/src/northbridge/intel/broadwell/broadwell.h +++ b/src/northbridge/intel/broadwell/broadwell.h @@ -25,7 +25,8 @@ #define MCH_BROADWELL_REV_E0 0x08 #define MCH_BROADWELL_REV_F0 0x09
-/* Device 0:0.0 PCI configuration space */ +/* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#define EPBAR 0x40 #define MCHBAR 0x48 @@ -60,24 +61,26 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) -#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ -#define DMAR_LCKDN (1 << 31) -#define PRSCAPDIS (1 << 2)
-#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ +#define REMAPBASE 0x90 /* Remap base */ +#define REMAPLIMIT 0x98 /* Remap limit */ +#define TOM 0xa0 /* Top of DRAM in memory controller space */ #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ #define BDSM 0xb0 /* Base Data Stolen Memory */ #define BGSM 0xb4 /* Base GTT Stolen Memory */ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ + #define SKPAD 0xdc /* Scratchpad Data */
+#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) + /* MCHBAR */
#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x)) @@ -89,7 +92,7 @@ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 -#define MCH_PAIR 0x5418 +#define INTRDIRCTL 0x5418 #define GDXCBAR 0x5420
#define MCH_PKG_POWER_LIMIT_LO 0x59a0 diff --git a/src/northbridge/intel/broadwell/igd.c b/src/northbridge/intel/broadwell/igd.c index b032782..f752638 100644 --- a/src/northbridge/intel/broadwell/igd.c +++ b/src/northbridge/intel/broadwell/igd.c @@ -24,7 +24,7 @@ #include <northbridge/intel/broadwell/igd.h> #include <types.h>
-#define GT_RETRY 1000 +#define GTT_RETRY 1000 enum { GT_CDCLK_DEFAULT = 0, GT_CDCLK_337, @@ -43,7 +43,7 @@ /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
/* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), @@ -104,10 +104,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
/* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
/* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -127,13 +127,13 @@
/* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
/* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY),
REG_SCRIPT_END }; @@ -141,7 +141,7 @@ static const struct reg_script broadwell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GTT_RETRY),
/* Enable push bus metric control and shift */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), @@ -206,10 +206,10 @@ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
/* Set RC6 VIDs */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GTT_RETRY),
/* Enable PM Interrupts */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), @@ -228,12 +228,12 @@
/* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GTT_RETRY),
/* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, - (1 << 30), (1 << 30), GT_RETRY), + (1 << 30), (1 << 30), GTT_RETRY),
REG_SCRIPT_END }; @@ -267,13 +267,15 @@ }
int gtt_poll(u32 reg, u32 mask, u32 value) -{ unsigned int try = GT_RETRY; +{ + unsigned int try = GTT_RETRY; u32 data;
while (try--) { data = gtt_read(reg); if ((data & mask) == value) return 1; + udelay(10); }
@@ -327,21 +329,22 @@ Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. Use 16 if we would have less than 100 steps otherwise. */ - const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + const unsigned int refclock = 24 * 1000 * 1000; + const unsigned int hz_limit = refclock / 128 / 100; unsigned int pwm_increment, pwm_period; u32 south_chicken2;
south_chicken2 = gtt_read(SOUTH_CHICKEN2); if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { pwm_increment = 16; - south_chicken2 |= 1 << 5; + south_chicken2 |= LPT_PWM_GRANULARITY; } else { pwm_increment = 128; - south_chicken2 &= ~(1 << 5); + south_chicken2 &= ~LPT_PWM_GRANULARITY; } gtt_write(SOUTH_CHICKEN2, south_chicken2);
- pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz; /* Start with a 50% duty cycle. */ gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
@@ -489,7 +492,7 @@ gtt_rmw(0x64810, 0xfffff800, dpdiv); }
-static void igd_init(struct device *dev) +static void gma_func0_init(struct device *dev) { int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); u32 rp1_gfx_freq; @@ -580,11 +583,11 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); }
-static struct device_operations igd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &igd_init, +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, .ops_pci = &broadwell_pci_ops, .acpi_fill_ssdt = gma_generate_ssdt, }; @@ -603,8 +606,8 @@ 0, };
-static const struct pci_driver igd_driver __pci_driver = { - .ops = &igd_ops, - .vendor = PCI_VENDOR_ID_INTEL, +static const struct pci_driver gma_driver __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/broadwell/minihd.c b/src/northbridge/intel/broadwell/minihd.c deleted file mode 100644 index 9df1047..0000000 --- a/src/northbridge/intel/broadwell/minihd.c +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/mmio.h> -#include <soc/intel/common/hda_verb.h> -#include <southbridge/intel/wildcatpoint/ramstage.h> -#include <northbridge/intel/broadwell/igd.h> - -static const u32 minihd_verb_table[] = { - /* coreboot specific header */ - 0x80862808, /* Codec Vendor / Device ID: Intel Broadwell Mini-HD */ - 0x80860101, /* Subsystem ID */ - 4, /* Number of jacks */ - - /* Enable 3rd Pin and Converter Widget */ - 0x00878101, - - /* Pin Widget 5 - PORT B */ - 0x00571c10, - 0x00571d00, - 0x00571e56, - 0x00571f18, - - /* Pin Widget 6 - PORT C */ - 0x00671c20, - 0x00671d00, - 0x00671e56, - 0x00671f18, - - /* Pin Widget 7 - PORT D */ - 0x00771c30, - 0x00771d00, - 0x00771e56, - 0x00771f18, - - /* Disable 3rd Pin and Converter Widget */ - 0x00878100, - - /* Dummy entries to fill out the table */ - 0x00878100, - 0x00878100, -}; - -static void minihd_init(struct device *dev) -{ - struct resource *res; - u32 reg32; - u8 *base; - int codec_mask, i; - - /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); - - /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* Mini-HD configuration */ - reg32 = read32(base + 0x100c); - reg32 &= 0xfffc0000; - reg32 |= 0x4; - write32(base + 0x100c, reg32); - - reg32 = read32(base + 0x1010); - reg32 &= 0xfffc0000; - reg32 |= 0x4b; - write32(base + 0x1010, reg32); - - /* Init the codec and write the verb table */ - codec_mask = hda_codec_detect(base); - - if (codec_mask) { - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - hda_codec_init(base, i, sizeof(minihd_verb_table), - minihd_verb_table); - } - } - - /* Set EM4/EM5 registers */ - write32(base + 0x0100c, igd_get_reg_em4()); - write32(base + 0x01010, igd_get_reg_em5()); -} - -static struct device_operations minihd_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = minihd_init, - .ops_pci = &broadwell_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x0a0c, /* Haswell */ - 0x160c, /* Broadwell */ - 0 -}; - -static const struct pci_driver minihd_driver __pci_driver = { - .ops = &minihd_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/northbridge/intel/broadwell/northbridge.c b/src/northbridge/intel/broadwell/northbridge.c index 480c17a..bf403f6 100644 --- a/src/northbridge/intel/broadwell/northbridge.c +++ b/src/northbridge/intel/broadwell/northbridge.c @@ -16,227 +16,8 @@ #include <southbridge/intel/wildcatpoint/ramstage.h> #include <northbridge/intel/broadwell/broadwell.h>
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 pciexbar_reg; - - *base = 0; - *len = 0; - - pciexbar_reg = pci_read_config32(dev, index); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; - case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; - case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - -static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = pci_read_config32(dev, index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -/* - * There are special BARs that actually are programmed in the MCHBAR. These Intel special - * features, but they do consume resources that need to be accounted for. - */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = MCHBAR32(index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -struct fixed_mmio_descriptor { - unsigned int index; - u32 size; - int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); - const char *description; -}; - -struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, - { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, - { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, - { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, -}; - -/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ -static void mc_add_fixed_mmio_resources(struct device *dev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { - u32 base; - u32 size; - struct resource *resource; - unsigned int index; - - size = mc_fixed_resources[i].size; - index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) - continue; - - resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - resource->base = base; - resource->size = size; - printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); - } -} - -/* Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal, making the size of the regions within 0. - * This is because the memory controller internally subtracts the base registers from each - * other to determine sizes of the regions. In other words, the memory map regions are always - * in a fixed order, no matter what sizes they have. - */ - -struct map_entry { - int reg; - int is_64_bit; - int is_limit; - const char *description; -}; - -static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) -{ - uint64_t value; - uint64_t mask; - - /* All registers have a 1MiB granularity */ - mask = ((1ULL << 20) - 1); - mask = ~mask; - - value = 0; - - if (entry->is_64_bit) { - value = pci_read_config32(dev, entry->reg + 4); - value <<= 32; - } - - value |= pci_read_config32(dev, entry->reg); - value &= mask; - - if (entry->is_limit) - value |= ~mask; - - *result = value; -} - -#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ - { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ - .is_limit = is_limit_, \ - .description = desc_, \ - } - -#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) -#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) - -enum { - TOM_REG, - TOUUD_REG, - MESEG_BASE_REG, - MESEG_LIMIT_REG, - REMAP_BASE_REG, - REMAP_LIMIT_REG, - TOLUD_REG, - BGSM_REG, - BDSM_REG, - TSEG_REG, - /* Must be last */ - NUM_MAP_ENTRIES, -}; - -static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), - [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), - [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), -}; - -static void mc_read_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - read_map_entry(dev, &memory_map[i], &values[i]); - } -} - -static void mc_report_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); - } - /* One can validate the BDSM and BGSM against the GGC */ - printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); -} +/* FIXME: For verification purposes only */ +#include <northbridge/intel/haswell/northbridge_common.c>
static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { @@ -248,8 +29,8 @@ struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/* Read in the MAP registers and report their values */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); + mc_read_map_entries(dev, mc_values); + mc_report_map_entries(dev, mc_values);
/* * DMA Protected Range can be reserved below TSEG for PCODE patch @@ -339,41 +120,20 @@ *resource_cnt = index; }
-static void mc_read_resources(struct device *dev) -{ - int index = 0; - const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - - /* Read standard PCI resources */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources */ - mc_add_fixed_mmio_resources(dev); - - /* Add VT-d MMIO resources, if capable */ - if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); - } - - /* Calculate and add DRAM resources */ - mc_add_dram_resources(dev, &index); -} - -static void systemagent_init(struct device *dev) +static void northbridge_init(struct device *dev) { struct soc_power_limits_config *config; u8 bios_reset_cpl, pair;
/* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(MCH_PAIR); + pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(MCH_PAIR) = pair; + MCHBAR8(INTRDIRCTL) = pair;
/* * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management + * that BIOS has initialized memory and power management. */ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); bios_reset_cpl |= 3; @@ -391,7 +151,7 @@ .acpi_fill_ssdt = generate_cpu_entries, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = systemagent_init, + .init = northbridge_init, .ops_pci = &broadwell_pci_ops, };
diff --git a/src/northbridge/intel/broadwell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl similarity index 78% rename from src/northbridge/intel/broadwell/acpi/ctdp.asl rename to src/northbridge/intel/haswell/acpi/ctdp.asl index 8391482..59fd37c 100644 --- a/src/northbridge/intel/broadwell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-Scope (_SB.PCI0.MCHC) -{ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ @@ -9,8 +7,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */
- OperationRegion (MCHB, SystemMemory, - Add (MCH_BASE_ADDRESS, 0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, Add (DEFAULT_MCHBAR, 0x5000), 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -62,17 +59,16 @@ External (_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (_SB.CP00._PSS), Local1) + Local0 = One /* Start at P1 */ + Local1 = SizeOf (_SB.CP00._PSS)
- While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ }
Return (0) @@ -81,9 +77,19 @@ /* Calculate PL2 based on chip type */ Method (CPL2, 1, NotSerialized) { +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) + If (\ISLP ()) { + /* Haswell ULT PL2 = 25W */ + Return (25 * 8) + } Else { + /* Haswell Mobile PL2 = 1.25 * PL1 */ + Return ((Arg0 * 125) / 100) + } +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) /* Haswell ULT PL2 = 25W */ /* FIXME: update for broadwell */ Return (Multiply (25, 8)) +#endif }
/* Set Config TDP Down */ @@ -100,23 +106,23 @@ Store ("Set TDP Down", Debug)
/* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD
/* Set TAR */ - Store (TARD, TARS) + TARS = TARD
/* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN ()
/* Set PL2 */ - Store (CPL2 (CTDD), PL2V) + PL2V = CPL2 (CTDD)
/* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD
/* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD
Release (CTCM) Return (1) @@ -128,7 +134,7 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } @@ -136,23 +142,23 @@ Store ("Set TDP Nominal", Debug)
/* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN
/* Set PL2 */ - Store (CPL2 (CTDN), PL2V) + PL2V = CPL2 (CTDN)
/* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN ()
/* Set TAR */ - Store (TARN, TARS) + TARS = TARN
/* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN
/* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN
Release (CTCM) Return (1) @@ -161,7 +167,7 @@ /* Calculate PL1 value based on requested TDP */ Method (TDPP, 1, NotSerialized) { - Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) + Return (((PUNI - 1) << 2) * Arg0) }
/* Enable Controllable TDP to limit PL1 to requested value */ @@ -174,19 +180,19 @@ Store ("Enable PL1 Limit", Debug)
/* Set _PPC to LFM */ - Store (PSSS (LFM_), Local0) - Add (Local0, 1, PPCM) + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 \PPCN ()
/* Set TAR to LFM-1 */ - Subtract (LFM_, 1, TARS) + TARS = LFM_ - 1
/* Set PL1 to desired value */ - Store (PL1V, SPL1) - Store (TDPP (Arg0), PL1V) + SPL1 = PL1V + PL1V = TDPP (Arg0)
/* Set PL1 CLAMP bit */ - Store (One, PL1C) + PL1C = 1
Release (CTCM) Return (1) @@ -202,19 +208,18 @@ Store ("Disable PL1 Limit", Debug)
/* Clear PL1 CLAMP bit */ - Store (Zero, PL1C) + PL1C = 0
/* Set PL1 to normal value */ - Store (SPL1, PL1V) + PL1V = SPL1
/* Set TAR to 0 */ - Store (Zero, TARS) + TARS = 0
/* Set _PPC to 0 */ - Store (Zero, PPCM) + PPCM = 0 \PPCN ()
Release (CTCM) Return (1) } -} diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debf..7ab47ac 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include "../haswell.h" + #include "hostbridge.asl" #include "peg.asl" #include <southbridge/intel/common/rcba.h> @@ -30,6 +31,6 @@ // Current Resource Settings Method (_CRS, 0, Serialized) { - Return(PDRS) + Return (PDRS) } } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index dd4b79a..5e694a6 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,18 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+Name (_HID, EISAID ("PNP0A08")) // PCIe +Name (_CID, EISAID ("PNP0A03")) // PCI
-Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) +Name (_BBN, 0)
Device (MCHC) { - Name(_ADR, 0x00000000) // 0:0.0 + Name (_ADR, 0x00000000) // 0:0.0
- OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) Offset (0x40), // EPBAR EPEN, 1, // Enable , 11, // @@ -34,10 +34,12 @@ DMEN, 1, // Enable , 11, // DMBR, 24, // DMIBAR +#endif
Offset (0x70), // ME Base Address MEBA, 64,
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) // ...
Offset (0x80), // PAM0 @@ -74,6 +76,7 @@ , 2, PM6H, 2, , 2, +#endif
Offset (0xa0), // Top of Used Memory TOM, 64, @@ -82,223 +85,9 @@ TLUD, 32, }
- Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ - Name (CTCC, 0) /* CTDP Current Selection */ - Name (CTCN, 0) /* CTDP Nominal Select */ - Name (CTCD, 1) /* CTDP Down Select */ - Name (CTCU, 2) /* CTDP Up Select */ - Name (SPL1, 0) /* Saved PL1 value */ - - OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) - Field (MCHB, DWordAcc, Lock, Preserve) - { - Offset (0x930), /* PACKAGE_POWER_SKU */ - CTDN, 15, /* CTDP Nominal PL1 */ - Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ - PUNI, 4, /* Power Units */ - , 4, - EUNI, 5, /* Energy Units */ - , 3, - TUNI, 4, /* Time Units */ - Offset (0x958), /* PLATFORM_INFO */ - , 40, - LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ - Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ - PL1V, 15, /* Power Limit 1 Value */ - PL1E, 1, /* Power Limit 1 Enable */ - PL1C, 1, /* Power Limit 1 Clamp */ - PL1T, 7, /* Power Limit 1 Time */ - Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ - PL2V, 15, /* Power Limit 2 Value */ - PL2E, 1, /* Power Limit 2 Enable */ - PL2C, 1, /* Power Limit 2 Clamp */ - PL2T, 7, /* Power Limit 2 Time */ - Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ - TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ - Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ - CTDD, 15, /* CTDP Down PL1 */ - , 1, - TARD, 8, /* CTDP Down Turbo Activation Ratio */ - Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ - CTDU, 15, /* CTDP Up PL1 */ - , 1, - TARU, 8, /* CTDP Up Turbo Activation Ratio */ - Offset (0xf50), /* CONFIG_TDP_CONTROL */ - CTCS, 2, /* CTDP Select */ - Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ - TARS, 8, /* Turbo Activation Ratio Select */ - } - - /* - * Search CPU0 _PSS looking for control = arg0 and then - * return previous P-state entry number for new _PPC - * - * Format of _PSS: - * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } - * } - */ - External (_SB.CP00._PSS) - Method (PSSS, 1, NotSerialized) - { - Local0 = One /* Start at P1 */ - Local1 = SizeOf (_SB.CP00._PSS) - - While (Local0 < Local1) { - /* Store _PSS entry Control value to Local2 */ - Local2 = DeRefOf (Index (DeRefOf (Index (_SB.CP00._PSS, Local0)), 4)) >> 8 - If (Local2 == Arg0) { - Return (Local0 - 1) - } - Local0++ - } - - Return (0) - } - - /* Calculate PL2 based on chip type */ - Method (CPL2, 1, NotSerialized) - { - If (\ISLP ()) { - /* Haswell ULT PL2 = 25W */ - Return (25 * 8) - } Else { - /* Haswell Mobile PL2 = 1.25 * PL1 */ - Return ((Arg0 * 125) / 100) - } - } - - /* Set Config TDP Down */ - Method (STND, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (LEqual (CTCD, CTCC)) { - Release (CTCM) - Return (0) - } - - Store ("Set TDP Down", Debug) - - /* Set CTC */ - CTCS = CTCD - - /* Set TAR */ - TARS = TARD - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARD) - PPCN () - - /* Set PL2 */ - PL2V = CPL2 (CTDD) - - /* Set PL1 */ - PL1V = CTDD - - /* Store the new TDP Down setting */ - CTCC = CTCD - - Release (CTCM) - Return (1) - } - - /* Set Config TDP Nominal from Down */ - Method (STDN, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCN == CTCC) { - Release (CTCM) - Return (0) - } - - Store ("Set TDP Nominal", Debug) - - /* Set PL1 */ - PL1V = CTDN - - /* Set PL2 */ - PL2V = CPL2 (CTDN) - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARN) - PPCN () - - /* Set TAR */ - TARS = TARN - - /* Set CTC */ - CTCS = CTCN - - /* Store the new TDP Nominal setting */ - CTCC = CTCN - - Release (CTCM) - Return (1) - } - - /* Calculate PL1 value based on requested TDP */ - Method (TDPP, 1, NotSerialized) - { - Return (((PUNI - 1) << 2) * Arg0) - } - - /* Enable Controllable TDP to limit PL1 to requested value */ - Method (CTLE, 1, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Store ("Enable PL1 Limit", Debug) - - /* Set _PPC to LFM */ - Local0 = PSSS (LFM_) - PPCM = Local0 + 1 - \PPCN () - - /* Set TAR to LFM-1 */ - TARS = LFM_ - 1 - - /* Set PL1 to desired value */ - SPL1 = PL1V - PL1V = TDPP (Arg0) - - /* Set PL1 CLAMP bit */ - PL1C = 1 - - Release (CTCM) - Return (1) - } - - /* Disable Controllable TDP */ - Method (CTLD, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Store ("Disable PL1 Limit", Debug) - - /* Clear PL1 CLAMP bit */ - PL1C = 0 - - /* Set PL1 to normal value */ - PL1V = SPL1 - - /* Set TAR to 0 */ - TARS = 0 - - /* Set _PPC to 0 */ - PPCM = 0 - \PPCN () - - Release (CTCM) - Return (1) - } +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) + #include "ctdp.asl" +#endif }
// Current Resource Settings @@ -440,7 +229,7 @@
PMIN = Local0 PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 - PLEN = PMAX - PMIN + 1 + PLEN = (PMAX - PMIN) + 1
Return (MCRS) } diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 41f18be..391d837 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -2,7 +2,13 @@
#include <arch/bootblock.h> #include <device/pci_ops.h> -#include "haswell.h" + +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) +#include <northbridge/intel/haswell/haswell.h> + +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) +#include <northbridge/intel/broadwell/broadwell.h> +#endif
void bootblock_early_northbridge_init(void) { diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 68072ff..42379d6 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -4,18 +4,18 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> -#include <console/console.h> #include <bootmode.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <drivers/intel/gma/i915_reg.h> -#include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/libgfxinit.h> -#include <cpu/intel/haswell/haswell.h> -#include <drivers/intel/gma/opregion.h> #include <string.h> +#include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/i915_reg.h> +#include <drivers/intel/gma/libgfxinit.h> +#include <drivers/intel/gma/opregion.h> +#include <cpu/intel/haswell/haswell.h> #include <types.h>
#include "chip.h" @@ -507,8 +507,8 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, - .acpi_fill_ssdt = gma_generate_ssdt, .ops_pci = &pci_dev_ops_pci, + .acpi_fill_ssdt = gma_generate_ssdt, };
static const unsigned short pci_device_ids[] = { @@ -527,7 +527,7 @@ 0, };
-static const struct pci_driver pch_lpc __pci_driver = { +static const struct pci_driver gma_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bd44168..db4d4d1 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -12,9 +12,14 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_MCHBAR 0xfed10000 /* 32 KB */ +#define MCH_BASE_SIZE 0x8000 + #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DMI_BASE_SIZE 0x1000 + #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define EP_BASE_SIZE 0x1000
#define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 @@ -22,6 +27,10 @@ #define VTVC0_BASE_ADDRESS 0xfed91000ULL #define VTVC0_BASE_SIZE 0x1000
+#define EDRAM_BASE_SIZE 0x4000 + +#define GDXC_BASE_SIZE 0x1000 + #include <southbridge/intel/lynxpoint/pch.h>
/* Everything below this line is ignored in the DSDT */ diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index de2ce06..00151db 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -6,11 +6,21 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> + +#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) #include <southbridge/intel/lynxpoint/hda_verb.h> +#define HDA_VENDEV_ID 0x80862807 + +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) +#include <soc/intel/common/hda_verb.h> +#include <southbridge/intel/wildcatpoint/ramstage.h> +#include <northbridge/intel/broadwell/igd.h> +#define HDA_VENDEV_ID 0x80862808 +#endif
static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862807, /* Codec Vendor / Device ID: Intel Haswell Mini-HD */ + HDA_VENDEV_ID, /* Codec Vendor / Device ID: Intel Haswell/Broadwell Mini-HD */ 0x80860101, /* Subsystem ID */ 4, /* Number of jacks */
@@ -82,6 +92,12 @@ minihd_verb_table); } } + +#if CONFIG(NORTHBRIDGE_INTEL_BROADWELL) + /* Set EM4/EM5 registers */ + write32(base + 0x0100c, igd_get_reg_em4()); + write32(base + 0x01010, igd_get_reg_em5()); +#endif }
static struct device_operations minihd_ops = { @@ -92,6 +108,7 @@ .ops_pci = &pci_dev_ops_pci, };
+#if CONFIG(NORTHBRIDGE_INTEL_HASWELL) static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 };
static const struct pci_driver haswell_minihd __pci_driver = { @@ -99,3 +116,18 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +#elif CONFIG(NORTHBRIDGE_INTEL_BROADWELL) +static const unsigned short pci_device_ids[] = { + 0x0a0c, /* Haswell */ + 0x160c, /* Broadwell */ + 0 +}; + +static const struct pci_driver minihd_driver __pci_driver = { + .ops = &minihd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif + diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ef7742e..cb9fe50 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -16,41 +16,6 @@ #include "chip.h" #include "haswell.h"
-static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 pciexbar_reg, mask; - - *base = 0; - *len = 0; - - pciexbar_reg = pci_read_config32(dev, index); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - *base = pciexbar_reg & mask; - *len = 256 * 1024 * 1024; - return 1; - case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - mask |= (1 << 27); - *base = pciexbar_reg & mask; - *len = 128 * 1024 * 1024; - return 1; - case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); - mask |= (1 << 27) | (1 << 26); - *base = pciexbar_reg & mask; - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -79,196 +44,8 @@ .write_acpi_tables = northbridge_write_acpi_tables, };
-static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = pci_read_config32(dev, index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -/* - * There are special BARs that actually are programmed in the MCHBAR. These Intel special - * features, but they do consume resources that need to be accounted for. - */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar = MCHBAR32(index); - - /* If not enabled don't report it */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit */ - *base = bar & ~1; - - return 1; -} - -struct fixed_mmio_descriptor { - unsigned int index; - u32 size; - int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); - const char *description; -}; - -#define SIZE_KB(x) ((x) * 1024) -struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, - { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, - { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, - { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, -}; -#undef SIZE_KB - -/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ -static void mc_add_fixed_mmio_resources(struct device *dev) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { - u32 base; - u32 size; - struct resource *resource; - unsigned int index; - - size = mc_fixed_resources[i].size; - index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) - continue; - - resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - resource->base = base; - resource->size = size; - printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); - } -} - -/* Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal, making the size of the regions within 0. - * This is because the memory controller internally subtracts the base registers from each - * other to determine sizes of the regions. In other words, the memory map regions are always - * in a fixed order, no matter what sizes they have. - */ - -struct map_entry { - int reg; - int is_64_bit; - int is_limit; - const char *description; -}; - -static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) -{ - uint64_t value; - uint64_t mask; - - /* All registers have a 1MiB granularity */ - mask = ((1ULL << 20) - 1); - mask = ~mask; - - value = 0; - - if (entry->is_64_bit) { - value = pci_read_config32(dev, entry->reg + 4); - value <<= 32; - } - - value |= pci_read_config32(dev, entry->reg); - value &= mask; - - if (entry->is_limit) - value |= ~mask; - - *result = value; -} - -#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ - { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ - .is_limit = is_limit_, \ - .description = desc_, \ - } - -#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) -#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) - -enum { - TOM_REG, - TOUUD_REG, - MESEG_BASE_REG, - MESEG_LIMIT_REG, - REMAP_BASE_REG, - REMAP_LIMIT_REG, - TOLUD_REG, - BGSM_REG, - BDSM_REG, - TSEG_REG, - /* Must be last */ - NUM_MAP_ENTRIES, -}; - -static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), - [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), - [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), -}; - -static void mc_read_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - read_map_entry(dev, &memory_map[i], &values[i]); - } -} - -static void mc_report_map_entries(struct device *dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); - } - /* One can validate the BDSM and BGSM against the GGC */ - printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); -} +/* FIXME: For verification purposes only */ +#include <northbridge/intel/haswell/northbridge_common.c>
static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { @@ -277,8 +54,8 @@ uint64_t mc_values[NUM_MAP_ENTRIES];
/* Read in the MAP registers and report their values */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); + mc_read_map_entries(dev, mc_values); + mc_report_map_entries(dev, mc_values);
/* * These are the host memory ranges that should be added: @@ -357,27 +134,6 @@ *resource_cnt = index; }
-static void mc_read_resources(struct device *dev) -{ - int index = 0; - const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - - /* Read standard PCI resources */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources */ - mc_add_fixed_mmio_resources(dev); - - /* Add VT-d MMIO resources, if capable */ - if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); - } - - /* Calculate and add DRAM resources */ - mc_add_dram_resources(dev, &index); -} - /* * The Mini-HD audio device is disabled whenever the IGD is. This is because it provides * audio over the integrated graphics port(s), which requires the IGD to be functional. @@ -422,7 +178,7 @@ { u8 bios_reset_cpl, pair;
- /* Enable Power Aware Interrupt Routing. */ + /* Enable Power Aware Interrupt Routing */ pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ @@ -439,7 +195,7 @@ MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
- /* Configure turbo power limits 1ms after reset complete bit. */ + /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); set_power_limits(28);
diff --git a/src/northbridge/intel/haswell/northbridge_common.c b/src/northbridge/intel/haswell/northbridge_common.c new file mode 100644 index 0000000..21a49ab --- /dev/null +++ b/src/northbridge/intel/haswell/northbridge_common.c @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file is being included from other C files! */ + +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + pciexbar_reg = pci_read_config32(dev, index); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: /* 256MB */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | + (1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | + (1 << 27) | (1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 bar = pci_read_config32(dev, index); + + /* If not enabled don't report it */ + if (!(bar & 1)) + return 0; + + /* Knock down the enable bit */ + *base = bar & ~1; + + return 1; +} + +/* + * There are special BARs that actually are programmed in the MCHBAR. These Intel special + * features, but they do consume resources that need to be accounted for. + */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) +{ + u32 bar = MCHBAR32(index); + + /* If not enabled don't report it */ + if (!(bar & 1)) + return 0; + + /* Knock down the enable bit */ + *base = bar & ~1; + + return 1; +} + +struct fixed_mmio_descriptor { + unsigned int index; + u32 size; + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); + const char *description; +}; + +struct fixed_mmio_descriptor mc_fixed_resources[] = { + { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, + { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, + { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, +}; + +/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ +static void mc_add_fixed_mmio_resources(struct device *dev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { + u32 base; + u32 size; + struct resource *resource; + unsigned int index; + + size = mc_fixed_resources[i].size; + index = mc_fixed_resources[i].index; + if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) + continue; + + resource = new_resource(dev, mc_fixed_resources[i].index); + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + + resource->base = base; + resource->size = size; + printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", + __func__, mc_fixed_resources[i].description, index, + (unsigned long)base, (unsigned long)(base + size - 1)); + } +} + +/* + * Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal, making the size of the regions within 0. + * This is because the memory controller internally subtracts the base registers from each + * other to determine sizes of the regions. In other words, the memory map regions are always + * in a fixed order, no matter what sizes they have. + */ + +struct map_entry { + int reg; + int is_64_bit; + int is_limit; + const char *description; +}; + +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) +{ + uint64_t value; + uint64_t mask; + + /* All registers have a 1MiB granularity */ + mask = ((1ULL << 20) - 1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + 4); + value <<= 32; + } + + value |= pci_read_config32(dev, entry->reg); + value &= mask; + + if (entry->is_limit) + value |= ~mask; + + *result = value; +} + +#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ + { \ + .reg = reg_, \ + .is_64_bit = is_64_, \ + .is_limit = is_limit_, \ + .description = desc_, \ + } + +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) + +enum { + TOM_REG, + TOUUD_REG, + MESEG_BASE_REG, + MESEG_LIMIT_REG, + REMAP_BASE_REG, + REMAP_LIMIT_REG, + TOLUD_REG, + BGSM_REG, + BDSM_REG, + TSEG_REG, + /* Must be last */ + NUM_MAP_ENTRIES, +}; + +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), +}; + +static void mc_read_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + read_map_entry(dev, &memory_map[i], &values[i]); + } +} + +static void mc_report_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } + /* One can validate the BDSM and BGSM against the GGC */ + printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); +} + +static void mc_add_dram_resources(struct device *dev, int *resource_cnt); + +static void mc_read_resources(struct device *dev) +{ + int index = 0; + const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + + /* Read standard PCI resources */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources */ + mc_add_fixed_mmio_resources(dev); + + /* Add VT-d MMIO resources, if capable */ + if (vtd_capable) { + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); + } + + /* Calculate and add DRAM resources */ + mc_add_dram_resources(dev, &index); +} diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8ea4175..d3c078f 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -22,7 +22,7 @@ if (cpuidr.eax < 0x80000004) { strcpy(cpu_string, "Platform info not available"); } else { - u32 *p = (u32*) cpu_string; + u32 *p = (u32 *)cpu_string; for (i = 2; i <= 4; i++) { cpuidr = cpuid(index + i); *p++ = cpuidr.eax; diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 0f59d70..1b6f0b2 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -9,23 +9,16 @@ */ static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); + u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(PCH_DEV_LPC, 0xdc, reg8); }
static void map_rcba(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); }
static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 291a554..cf2a5f7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -189,6 +189,7 @@
/* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define PCH_DEV_LPC PCH_LPC_DEV #define SERIRQ_CNTL 0x64
#define GEN_PMCON_1 0xa0 diff --git a/src/southbridge/intel/wildcatpoint/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c index 55bb1c3..1e27ed6 100644 --- a/src/southbridge/intel/wildcatpoint/bootblock.c +++ b/src/southbridge/intel/wildcatpoint/bootblock.c @@ -25,7 +25,7 @@
static void map_rcba(void) { - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); }
static void enable_port80_on_lpc(void) @@ -43,18 +43,18 @@ u8 ssfc;
/* Observe SPI Descriptor Component Section 0 */ - SPIBAR32(SPIBAR_FDOC) = 0x1000; + SPIBAR32(FDOC) = 0x1000;
/* Extract the Write/Erase SPI Frequency from descriptor */ - fdod = SPIBAR32(SPIBAR_FDOD); + fdod = SPIBAR32(FDOD); fdod >>= 24; fdod &= 7;
/* Set Software Sequence frequency to match */ - ssfc = SPIBAR8(SPIBAR_SSFC + 2); + ssfc = SPIBAR8(SSFC + 2); ssfc &= ~7; ssfc |= fdod; - SPIBAR8(SPIBAR_SSFC + 2) = ssfc; + SPIBAR8(SSFC + 2) = ssfc; }
const struct reg_script pch_early_init_script[] = { diff --git a/src/southbridge/intel/wildcatpoint/iomap.h b/src/southbridge/intel/wildcatpoint/iomap.h index 241569e..37e62bb 100644 --- a/src/southbridge/intel/wildcatpoint/iomap.h +++ b/src/southbridge/intel/wildcatpoint/iomap.h @@ -9,6 +9,9 @@ #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000
+/* Haswell uses this name */ +#define DEFAULT_MCHBAR MCH_BASE_ADDRESS + #define DMI_BASE_ADDRESS 0xfed18000 #define DMI_BASE_SIZE 0x1000
@@ -24,6 +27,9 @@ #define RCBA_BASE_ADDRESS 0xfed1c000 #define RCBA_BASE_SIZE 0x4000
+/* Lynxpoint uses this name */ +#define DEFAULT_RCBA RCBA_BASE_ADDRESS + #define HPET_BASE_ADDRESS 0xfed00000
#define GFXVT_BASE_ADDRESS 0xfed90000ULL diff --git a/src/southbridge/intel/wildcatpoint/pch.c b/src/southbridge/intel/wildcatpoint/pch.c index efee415..f449c69 100644 --- a/src/southbridge/intel/wildcatpoint/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -48,15 +48,15 @@ { u32 fdoc;
- fdoc = SPIBAR32(SPIBAR_FDOC); + fdoc = SPIBAR32(FDOC); fdoc &= ~0x00007ffc; - SPIBAR32(SPIBAR_FDOC) = fdoc; + SPIBAR32(FDOC) = fdoc;
fdoc |= 0x00004000; fdoc |= id * 4; - SPIBAR32(SPIBAR_FDOC) = fdoc; + SPIBAR32(FDOC) = fdoc;
- return SPIBAR32(SPIBAR_FDOD); + return SPIBAR32(FDOD); }
#ifndef __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/wildcatpoint/spi.h b/src/southbridge/intel/wildcatpoint/spi.h index 726b37e..8851f65 100644 --- a/src/southbridge/intel/wildcatpoint/spi.h +++ b/src/southbridge/intel/wildcatpoint/spi.h @@ -13,9 +13,9 @@ #define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET)
/* Registers within the SPIBAR */ -#define SPIBAR_SSFC 0x91 -#define SPIBAR_FDOC 0xb0 -#define SPIBAR_FDOD 0xb4 +#define SSFC 0x91 +#define FDOC 0xb0 +#define FDOD 0xb4
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
Hello Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42626
to look at the new patch set (#3).
Change subject: Merge Haswell and Broadwell files ......................................................................
Merge Haswell and Broadwell files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same.
Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c D src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell_init.c D src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/haswell/acpi.c A src/cpu/intel/haswell/acpi_common.c M src/cpu/intel/haswell/bootblock.c A src/cpu/intel/haswell/cstate_def.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c A src/cpu/intel/haswell/hsw_bdw_init_common.c M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/broadwell/Makefile.inc M src/northbridge/intel/broadwell/acpi/broadwell.asl D src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/igd.c D src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c R src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c A src/northbridge/intel/haswell/northbridge_common.c M src/northbridge/intel/haswell/report_platform.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/spi.h 36 files changed, 1,129 insertions(+), 2,636 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42626/3/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge_common.c:
https://review.coreboot.org/c/coreboot/+/42626/3/src/northbridge/intel/haswe... PS3, Line 211: for (i = 0; i < NUM_MAP_ENTRIES; i++) { braces {} are not necessary for single statement blocks
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42626
to look at the new patch set (#4).
Change subject: Merge Haswell and Broadwell files ......................................................................
Merge Haswell and Broadwell files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same.
Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c D src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell_init.c D src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/haswell/acpi.c A src/cpu/intel/haswell/acpi_common.c M src/cpu/intel/haswell/bootblock.c A src/cpu/intel/haswell/cstate_def.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c A src/cpu/intel/haswell/hsw_bdw_init_common.c M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/broadwell/Makefile.inc M src/northbridge/intel/broadwell/acpi/broadwell.asl D src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/igd.c D src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c R src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c A src/northbridge/intel/haswell/northbridge_common.c M src/northbridge/intel/haswell/report_platform.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/spi.h 36 files changed, 1,129 insertions(+), 2,636 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/4
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42626
to look at the new patch set (#7).
Change subject: Merge Haswell and Broadwell files ......................................................................
Merge Haswell and Broadwell files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same.
Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c D src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell_init.c D src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/haswell/acpi.c A src/cpu/intel/haswell/acpi_common.c M src/cpu/intel/haswell/bootblock.c A src/cpu/intel/haswell/cstate_def.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c A src/cpu/intel/haswell/hsw_bdw_init_common.c M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/broadwell/Makefile.inc M src/northbridge/intel/broadwell/acpi/broadwell.asl D src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/igd.c D src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c R src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c A src/northbridge/intel/haswell/northbridge_common.c M src/northbridge/intel/haswell/report_platform.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/spi.h 36 files changed, 1,129 insertions(+), 2,636 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42626
to look at the new patch set (#8).
Change subject: Merge Haswell and Broadwell files ......................................................................
Merge Haswell and Broadwell files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same.
Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c D src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell_init.c D src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/haswell/acpi.c A src/cpu/intel/haswell/acpi_common.c M src/cpu/intel/haswell/bootblock.c A src/cpu/intel/haswell/cstate_def.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c A src/cpu/intel/haswell/hsw_bdw_init_common.c M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/broadwell/Makefile.inc M src/northbridge/intel/broadwell/acpi/broadwell.asl D src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/igd.c D src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c R src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c A src/northbridge/intel/haswell/northbridge_common.c M src/northbridge/intel/haswell/report_platform.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/spi.h 37 files changed, 1,156 insertions(+), 2,661 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42626/10/src/northbridge/intel/hasw... File src/northbridge/intel/haswell/northbridge_common.c:
https://review.coreboot.org/c/coreboot/+/42626/10/src/northbridge/intel/hasw... PS10, Line 211: for (i = 0; i < NUM_MAP_ENTRIES; i++) { braces {} are not necessary for single statement blocks
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42626
to look at the new patch set (#11).
Change subject: Merge Haswell and Broadwell files ......................................................................
Merge Haswell and Broadwell files
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains the same.
Change-Id: I72e8efc465ebe44ea9b1baaca2a317a29eb9506d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/broadwell/Makefile.inc M src/cpu/intel/broadwell/acpi.c D src/cpu/intel/broadwell/bootblock.c M src/cpu/intel/broadwell/broadwell_init.c D src/cpu/intel/broadwell/smmrelocate.c M src/cpu/intel/haswell/acpi.c A src/cpu/intel/haswell/acpi_common.c M src/cpu/intel/haswell/bootblock.c A src/cpu/intel/haswell/cstate_def.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c A src/cpu/intel/haswell/hsw_bdw_init_common.c M src/cpu/intel/haswell/smmrelocate.c M src/northbridge/intel/broadwell/Makefile.inc M src/northbridge/intel/broadwell/acpi/broadwell.asl D src/northbridge/intel/broadwell/bootblock.c M src/northbridge/intel/broadwell/broadwell.h M src/northbridge/intel/broadwell/igd.c D src/northbridge/intel/broadwell/minihd.c M src/northbridge/intel/broadwell/northbridge.c R src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c A src/northbridge/intel/haswell/northbridge_common.c M src/northbridge/intel/haswell/report_platform.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/wildcatpoint/bootblock.c M src/southbridge/intel/wildcatpoint/iomap.h M src/southbridge/intel/wildcatpoint/pch.c M src/southbridge/intel/wildcatpoint/spi.h 37 files changed, 1,153 insertions(+), 2,652 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42626/11
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42626/11/src/northbridge/intel/hasw... File src/northbridge/intel/haswell/northbridge_common.c:
https://review.coreboot.org/c/coreboot/+/42626/11/src/northbridge/intel/hasw... PS11, Line 211: for (i = 0; i < NUM_MAP_ENTRIES; i++) { braces {} are not necessary for single statement blocks
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files ......................................................................
Patch Set 11:
This is the error:
#!!!!! Error: CONFIG() used on unknown value (SOC_INTEL_BROADWELL) at src/soc/intel/common/block/cpu/cpulib.c:281.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files ......................................................................
Patch Set 11:
Patch Set 11:
This is the error:
#!!!!! Error: CONFIG() used on unknown value (SOC_INTEL_BROADWELL) at src/soc/intel/common/block/cpu/cpulib.c:281.
grml, cursed soc/intel
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42626 )
Change subject: Merge Haswell and Broadwell files ......................................................................
Abandoned
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Paul Menzel (Code Review)