Patch merged into coreboot/master: 2663a55 samus: Combine mainboard patches to build soc/intel/broadwell

the following patch was just integrated into master:
commit 2663a55caf2c04c0ee8793c3ac3ccaa63ab4da6c
Author: Duncan Laurie 
Date:   Wed May 14 15:59:37 2014 -0700

samus: Combine mainboard patches to build soc/intel/broadwell

Combine four patches dependencies. These will not build
    individually, so combine them for coreboot.org upstream.

samus: Move SPD handling to separate file

The code to find the SPD data for the mainboard based on GPIOs
    is moved from romstage.c into spd.c.

It relies on the updated pei_data structure from broadwell instead
    of the haswell interface.

BUG=chrome-os-partner:28234
    TEST=Build and boot on samus
    CQ-DEPEND=CL:199921
    CQ-DEPEND=CL:199922
    CQ-DEPEND=CL:199923
    CQ-DEPEND=CL:199943
    CQ-DEPEND=CL:*163751

Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c
    Original-Signed-off-by: Duncan Laurie 
    Original-Reviewed-on: https://chromium-review.googlesource.com/199920
    Original-Reviewed-by: Aaron Durbin 
    (cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62)
    Signed-off-by: Marc Jones

samus: Move PEI data structure init to separate file

This needs to be executed in both romstage and ramstage
    for the different PEI binary stages.

It uses the broadwell interface now instead of haswell.

BUG=chrome-os-partner:28234
    TEST=Build and boot on samus
    CQ-DEPEND=CL:199920
    CQ-DEPEND=CL:199922
    CQ-DEPEND=CL:199923
    CQ-DEPEND=CL:199943
    CQ-DEPEND=CL:*163751

Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
    Original-Signed-off-by: Duncan Laurie 
    Original-Reviewed-on: https://chromium-review.googlesource.com/199921
    (cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de)
    Signed-off-by: Marc Jones

samus: Convert mainboard to use soc/intel/broadwell

Switch from the haswell cpu/northbridge/southbridge interface
    to the soc/intel/broadwell interface.

- Use new headers where appropriate
    - Remove code that is now done by the SOC generic code
    - Update GPIO map to drop LP specific handling
    - Update INT15 handlers, drop all but the boot display hook

BUG=chrome-os-partner:28234
    TEST=Build and boot on samus
    CQ-DEPEND=CL:199920
    CQ-DEPEND=CL:199921
    CQ-DEPEND=CL:199923
    CQ-DEPEND=CL:199943
    CQ-DEPEND=CL:*163751

Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
    Original-Signed-off-by: Duncan Laurie 
    Original-Reviewed-on: https://chromium-review.googlesource.com/199922

(cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375)
    Signed-off-by: Marc Jones

samus: Add some code to print basic info from SPD

The handling of LPDDR is a bit messy in Intel platforms.  There
    is no traditional SPD so instead one is created by hand from the
    provided datasheets.

These have varying (and sometimes unexpected) geometry and it can
    be important during bringup to know what configuration is being
    passed to the memory training code.

This could in theory be put in a more generic location, but for now
    this is the only board with LPDDR3 where I have found it valuable.

BUG=chrome-os-partner:28234
    TEST=Build and boot on samus, look for SPD details on the console.
    CQ-DEPEND=CL:199920
    CQ-DEPEND=CL:199921
    CQ-DEPEND=CL:199922
    CQ-DEPEND=CL:199943
    CQ-DEPEND=CL:*163751

Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259
    Original-Signed-off-by: Duncan Laurie 
    Original-Reviewed-on: https://chromium-review.googlesource.com/199923
    (cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab)
    Signed-off-by: Marc Jones

Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d
    Reviewed-on: http://review.coreboot.org/7943
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan

See http://review.coreboot.org/7943 for details.

-gerrit