Change in coreboot[master]: soc/intel/alderlake: Fix build failure with enabled CSE stitching

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58515 )

Change subject: soc/intel/alderlake: Fix build failure with enabled CSE stitching
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soc/intel/alderlake: Fix build failure with enabled CSE stitching

The following error is observed when building coreboot with CSE stitching
enabled.

`src/soc/intel/alderlake/Makefile.inc:62: *** missing separator.  Stop.`

This change prevents such error.

BUG=None
TEST=Enable CSE stitching, build should complete successfully.

Change-Id: I1d9f442d1e1e7be4e8bbd1e653ed0ae6b7475f45
Signed-off-by: Bernardo Perez Priego 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58515
Tested-by: build bot (Jenkins) 
Reviewed-by: Selma Bensaid 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Makefile.inc
1 file changed, 17 insertions(+), 17 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Selma Bensaid: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index 00d857c..a11352f 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -59,23 +59,23 @@

ifeq ($(CONFIG_STITCH_ME_BIN),y)

-$(call cse_add_dummy_to_bp1_bp2,DLMP)
-$(call cse_add_dummy_to_bp1_bp2,IFPP)
-$(call cse_add_dummy_to_bp1_bp2,SBDT)
-$(call cse_add_decomp_to_bp1_bp2,RBEP)
-$(call cse_add_dummy_to_bp1_bp2,UFSP)
-$(call cse_add_dummy_to_bp1_bp2,UFSG)
-$(call cse_add_dummy_to_bp1_bp2,OEMP)
-$(call cse_add_input_to_bp1_bp2,PMCP)
-$(call cse_add_decomp,bp1,MFTP)
-$(call cse_add_decomp,bp2,FTPR)
-$(call cse_add_input_to_bp1_bp2,IOMP)
-$(call cse_add_input_to_bp1_bp2,NPHY)
-$(call cse_add_input_to_bp1_bp2,TBTP)
-$(call cse_add_input_to_bp1_bp2,PCHC)
-$(call cse_add_decomp,bp2,NFTP)
-$(call cse_add_dummy,bp2,ISHP)
-$(call cse_add_input,bp2,IUNP)
+$(eval $(call cse_add_dummy_to_bp1_bp2,DLMP))
+$(eval $(call cse_add_dummy_to_bp1_bp2,IFPP))
+$(eval $(call cse_add_dummy_to_bp1_bp2,SBDT))
+$(eval $(call cse_add_decomp_to_bp1_bp2,RBEP))
+$(eval $(call cse_add_dummy_to_bp1_bp2,UFSP))
+$(eval $(call cse_add_dummy_to_bp1_bp2,UFSG))
+$(eval $(call cse_add_dummy_to_bp1_bp2,OEMP))
+$(eval $(call cse_add_input_to_bp1_bp2,PMCP))
+$(eval $(call cse_add_decomp,bp1,MFTP))
+$(eval $(call cse_add_decomp,bp2,FTPR))
+$(eval $(call cse_add_input_to_bp1_bp2,IOMP))
+$(eval $(call cse_add_input_to_bp1_bp2,NPHY))
+$(eval $(call cse_add_input_to_bp1_bp2,TBTP))
+$(eval $(call cse_add_input_to_bp1_bp2,PCHC))
+$(eval $(call cse_add_decomp,bp2,NFTP))
+$(eval $(call cse_add_dummy,bp2,ISHP))
+$(eval $(call cse_add_input,bp2,IUNP))

endif