Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
md/cedarisland_crb: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. However, the PAD_CFG_GPO_GPIO_DRIVER() macros are still used, since these macros were added to the project for a long time ago and some motherboards use them in the configuration. The issue related to these macros should be resolved in a separate patch.
[1] https: //review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 240 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40736/1
diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index 6aca58d..e87b728 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -11,533 +11,533 @@ /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - ESPI_ALERT1# */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF3, TX_DISABLE, OFF), /* GPP_A1 - ESPI_IO0 */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A2 - ESPI_IO1 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000c02, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A3 - ESPI_IO2 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A4 - ESPI_IO3 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A5 - ESPI_CS0# */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000e00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A5, 20K_PU, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A6 - ESPI_CS1# */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A7 - ESPI_ALERT0# */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000d02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF3, TX_DISABLE, OFF), /* GPP_A8 - CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000400, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A9 - ESPI_CLK */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000e00, 0x00001010), + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A10 - CLKOUT_LPC1 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A11 - GPIO */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ - _PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000), + PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), /* GPP_A13 - GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 0, DEEP, NONE), /* GPP_A14 - ESPI_RESET# */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A15 - GPIO */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x00000010), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A16, 1, DEEP, NONE), /* GPP_A17 - GPIO */ - _PAD_CFG_STRUCT(GPP_A17, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, RSMRST, OFF, ACPI), /* GPP_A18 - GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, RSMRST, OFF, ACPI), /* GPP_A19 - RESERVED */ /* GPP_A20 - GPIO */ - _PAD_CFG_STRUCT(GPP_A20, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, RSMRST, OFF, ACPI), /* GPP_A21 - GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, RSMRST, OFF, ACPI), /* GPP_A22 - GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, RSMRST, OFF, ACPI), /* GPP_A23 - GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B0, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B1 - CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B1, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B2 - GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI), /* GPP_B3 - GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, RSMRST, OFF, ACPI), /* GPP_B4 - GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, RSMRST, OFF, ACPI), /* GPP_B5 - GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, RSMRST, OFF, ACPI), /* GPP_B6 - GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, RSMRST, OFF, ACPI), /* GPP_B7 - GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, RSMRST, OFF, ACPI), /* GPP_B8 - GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, RSMRST, OFF, ACPI), /* GPP_B9 - GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, RSMRST, OFF, ACPI), /* GPP_B10 - GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, RSMRST, OFF, ACPI), /* GPP_B11 - RESERVED */ /* GPP_B12 - GPIO */ - _PAD_CFG_STRUCT(GPP_B12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, RSMRST, OFF, ACPI), /* GPP_B13 - PLTRST# */ - _PAD_CFG_STRUCT(GPP_B13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B14 - SPKR */ - _PAD_CFG_STRUCT(GPP_B14, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_B15 - GPIO */ - _PAD_CFG_STRUCT(GPP_B15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI), /* GPP_B16 - GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, RSMRST, OFF, ACPI), /* GPP_B17 - GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, RSMRST, OFF, ACPI), /* GPP_B18 - GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, RSMRST, OFF, ACPI), /* GPP_B19 - GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, RSMRST, OFF, ACPI), /* GPP_B20 - GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_B20, 0, RSMRST), /* GPP_B21 - GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, RSMRST, OFF, ACPI), /* GPP_B22 - GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, 0x04000a00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, OFF),
/* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - SATAXPCIE3 */ - _PAD_CFG_STRUCT(GPP_F0, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F0, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F1 - SATAXPCIE4 */ - _PAD_CFG_STRUCT(GPP_F1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F2 - SATAXPCIE5 */ - _PAD_CFG_STRUCT(GPP_F2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F3 - SATAXPCIE6 */ - _PAD_CFG_STRUCT(GPP_F3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F4 - SATAXPCIE7 */ - _PAD_CFG_STRUCT(GPP_F4, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F4, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPP_F6 - GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F6, 0, RSMRST), /* GPP_F7 - GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* GPP_F8 - GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F8, 0, RSMRST), /* GPP_F9 - GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI), /* GPP_F10 - SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F11 - SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F12 - SATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_F12, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F13 - SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F14 - SSATA_LED# */ - _PAD_CFG_STRUCT(GPP_F14, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_F15 - USB_OC4# */ - _PAD_CFG_STRUCT(GPP_F15, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F16 - USB_OC5# */ - _PAD_CFG_STRUCT(GPP_F16, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F17 - USB_OC6# */ - _PAD_CFG_STRUCT(GPP_F17, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F18 - USB_OC7# */ - _PAD_CFG_STRUCT(GPP_F18, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F18, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F19 - LAN_SMBCLK */ - _PAD_CFG_STRUCT(GPP_F19, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_F20 - LAN_SMBDATA */ - _PAD_CFG_STRUCT(GPP_F20, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_F21 - GPIO */ - _PAD_CFG_STRUCT(GPP_F21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, RSMRST, OFF, ACPI), /* GPP_F22 - SSATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F22, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_F23 - SSATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F23, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, RSMRST, NF3, RX_DISABLE, OFF),
/* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - GPIO */ - _PAD_CFG_STRUCT(GPP_C2, 0x00000102, 0x00000000), + PAD_CFG_GPI(GPP_C2, NONE, RSMRST), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - SML0ALERT# */ - _PAD_CFG_STRUCT(GPP_C5, 0x04000602, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_C5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - _PAD_CFG_STRUCT(GPP_C8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, RSMRST, OFF, ACPI), /* GPP_C9 - GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x04000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, DRIVER), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_C11 - GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, RSMRST, OFF, ACPI), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, RSMRST, OFF, ACPI), /* GPP_C14 - GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, RSMRST, OFF, ACPI), /* GPP_C15 - GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, RSMRST, OFF, ACPI), /* GPP_C16 - GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, RSMRST, OFF, ACPI), /* GPP_C17 - GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, RSMRST, OFF, ACPI), /* GPP_C18 - GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, RSMRST, OFF, ACPI), /* GPP_C19 - GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_C19, 0, RSMRST), /* GPP_C20 - RESERVED */ /* GPP_C21 - GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_C21, 0, RSMRST), /* GPP_C22 - GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, RSMRST, OFF, ACPI), /* GPP_C23 - GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - _PAD_CFG_STRUCT(GPP_D0, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, RSMRST, OFF, ACPI), /* GPP_D1 - GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D1, 0, RSMRST), /* GPP_D2 - GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D2, 0, RSMRST), /* GPP_D3 - GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, RSMRST, OFF, ACPI), /* GPP_D4 - GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x04000201, 0x00000000), + PAD_CFG_GPO(GPP_D4, 1, RSMRST), /* GPP_D5 - GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, RSMRST, OFF, ACPI), /* GPP_D6 - GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x04000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, DRIVER), /* GPP_D7 - GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI), /* GPP_D8 - GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, RSMRST, OFF, ACPI), /* GPP_D9 - GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI), /* GPP_D10 - SSATA_DEVSLP4 */ - _PAD_CFG_STRUCT(GPP_D10, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D10, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D11 - GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, RSMRST, OFF, ACPI), /* GPP_D12 - SSATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_D12, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D12, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D13 - SML0BCLK_IE */ - _PAD_CFG_STRUCT(GPP_D13, 0x04000c02, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D13, NONE, RSMRST, NF3, NO_DISABLE, OFF), /* GPP_D14 - SML0BDATA_IE */ - _PAD_CFG_STRUCT(GPP_D14, 0x04000c02, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D14, NONE, RSMRST, NF3, NO_DISABLE, OFF), /* GPP_D15 - SSATA_SDATAOUT0 */ - _PAD_CFG_STRUCT(GPP_D15, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D16 - GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPP_D17 - GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D17, 0, RSMRST), /* GPP_D18 - GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, RSMRST, OFF, ACPI), /* GPP_D19 - GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D19, 0, RSMRST), /* GPP_D20 - GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, RSMRST, OFF, ACPI), /* GPP_D21 - GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, RSMRST, OFF, ACPI), /* GPP_D22 - GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), /* GPP_D23 - GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - _PAD_CFG_STRUCT(GPP_E0, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E1 - SATAXPCIE1 */ - _PAD_CFG_STRUCT(GPP_E1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E2 - SATAXPCIE2 */ - _PAD_CFG_STRUCT(GPP_E2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E3 - CPU_GP0 */ - _PAD_CFG_STRUCT(GPP_E3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E4 - GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, RSMRST, OFF, ACPI), /* GPP_E5 - GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, RSMRST, OFF, ACPI), /* GPP_E6 - GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, RSMRST, OFF, ACPI), /* GPP_E7 - GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x40840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT), /* GPP_E8 - SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E8, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_E9 - USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E9, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E10 - USB_OC1# */ - _PAD_CFG_STRUCT(GPP_E10, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E11 - USB_OC2# */ - _PAD_CFG_STRUCT(GPP_E11, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E12 - USB_OC3# */ - _PAD_CFG_STRUCT(GPP_E12, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, RSMRST, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - ACPRESENT */ - _PAD_CFG_STRUCT(GPD1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD2 - GBE_WAKE# */ - _PAD_CFG_STRUCT(GPD2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD3 - PWRBTN# */ - _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD4 - SLP_S3# */ - _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD5 - SLP_S4# */ - _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD6 - SLP_A# */ - _PAD_CFG_STRUCT(GPD6, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD6, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ - _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - SLP_S5# */ - _PAD_CFG_STRUCT(GPD10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD11 - GBEPHY */ - _PAD_CFG_STRUCT(GPD11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, RX_DISABLE, OFF),
/* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - _PAD_CFG_STRUCT(GPP_I0, 0x04000a00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, RSMRST, NF2, RX_DISABLE, OFF), /* GPP_I1 - LAN_TCK */ - _PAD_CFG_STRUCT(GPP_I1, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I2 - LAN_TMS */ - _PAD_CFG_STRUCT(GPP_I2, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I3 - LAN_TDI */ - _PAD_CFG_STRUCT(GPP_I3, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_I5 - GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_I5, 0, RSMRST), /* GPP_I6 - GPIO */ - _PAD_CFG_STRUCT(GPP_I6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI), /* GPP_I7 - LAN_TRST_IN */ - _PAD_CFG_STRUCT(GPP_I7, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I8 - PCI_DIS */ - _PAD_CFG_STRUCT(GPP_I8, 0x04000900, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I9 - LAN_DIS */ - _PAD_CFG_STRUCT(GPP_I9, 0x04000900, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I10 - GPIO */ - _PAD_CFG_STRUCT(GPP_I10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - GPIO */ - _PAD_CFG_STRUCT(GPP_J0, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J0, 0, RSMRST), /* GPP_J1 - GPIO */ - _PAD_CFG_STRUCT(GPP_J1, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J1, 0, RSMRST), /* GPP_J2 - GPIO */ - _PAD_CFG_STRUCT(GPP_J2, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J2, 0, RSMRST), /* GPP_J3 - GPIO */ - _PAD_CFG_STRUCT(GPP_J3, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J3, 0, RSMRST), /* GPP_J4 - GPIO */ - _PAD_CFG_STRUCT(GPP_J4, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J4, 0, RSMRST), /* GPP_J5 - GPIO */ - _PAD_CFG_STRUCT(GPP_J5, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J5, 0, RSMRST), /* GPP_J6 - GPIO */ - _PAD_CFG_STRUCT(GPP_J6, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J6, 0, RSMRST), /* GPP_J7 - GPIO */ - _PAD_CFG_STRUCT(GPP_J7, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J7, 0, RSMRST), /* GPP_J8 - GPIO */ - _PAD_CFG_STRUCT(GPP_J8, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J8, 0, RSMRST), /* GPP_J9 - GPIO */ - _PAD_CFG_STRUCT(GPP_J9, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J9, 0, RSMRST), /* GPP_J10 - GPIO */ - _PAD_CFG_STRUCT(GPP_J10, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J10, 0, RSMRST), /* GPP_J11 - GPIO */ - _PAD_CFG_STRUCT(GPP_J11, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J11, 0, RSMRST), /* GPP_J12 - GPIO */ - _PAD_CFG_STRUCT(GPP_J12, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J12, 0, RSMRST), /* GPP_J13 - GPIO */ - _PAD_CFG_STRUCT(GPP_J13, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_J14 - GPIO */ - _PAD_CFG_STRUCT(GPP_J14, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J14, 0, RSMRST), /* GPP_J15 - GPIO */ - _PAD_CFG_STRUCT(GPP_J15, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_J16 - GPIO */ - _PAD_CFG_STRUCT(GPP_J16, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J16, 0, RSMRST), /* GPP_J17 - GPIO */ - _PAD_CFG_STRUCT(GPP_J17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, RSMRST, OFF, ACPI), /* GPP_J18 - GPIO */ - _PAD_CFG_STRUCT(GPP_J18, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J18, 0, RSMRST), /* GPP_J19 - GPIO */ - _PAD_CFG_STRUCT(GPP_J19, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, RSMRST, OFF, ACPI), /* GPP_J20 - GPIO */ - _PAD_CFG_STRUCT(GPP_J20, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J20, 0, RSMRST), /* GPP_J21 - GPIO */ - _PAD_CFG_STRUCT(GPP_J21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, RSMRST, OFF, ACPI), /* GPP_J22 - GPIO */ - _PAD_CFG_STRUCT(GPP_J22, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J22, 0, RSMRST), /* GPP_J23 - GPIO */ - _PAD_CFG_STRUCT(GPP_J23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - LAN_NCSI_CLK_IN */ - _PAD_CFG_STRUCT(GPP_K0, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K0, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_K1 - LAN_NCSI_TXD0 */ - _PAD_CFG_STRUCT(GPP_K1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K2 - LAN_NCSI_TXD1 */ - _PAD_CFG_STRUCT(GPP_K2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K3 - LAN_NCSI_TX_EN */ - _PAD_CFG_STRUCT(GPP_K3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K4 - LAN_NCSI_CRS_DV */ - _PAD_CFG_STRUCT(GPP_K4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_K5 - LAN_NCSI_RXD0 */ - _PAD_CFG_STRUCT(GPP_K5, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K5, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K6 - LAN_NCSI_RXD1 */ - _PAD_CFG_STRUCT(GPP_K6, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K6, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K7 - RESERVED */ - _PAD_CFG_STRUCT(GPP_K7, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_K8 - LAN_NCSI_ARB_IN */ - _PAD_CFG_STRUCT(GPP_K8, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - _PAD_CFG_STRUCT(GPP_K9, 0x04000602, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_K10 - PE_RST# */ - _PAD_CFG_STRUCT(GPP_K10, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, RSMRST, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - _PAD_CFG_STRUCT(GPP_G0, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, RSMRST, OFF, ACPI), /* GPP_G1 - GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, RSMRST, OFF, ACPI), /* GPP_G2 - GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, RSMRST, OFF, ACPI), /* GPP_G3 - GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, RSMRST, OFF, ACPI), /* GPP_G4 - GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, RSMRST, OFF, ACPI), /* GPP_G5 - GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, RSMRST, OFF, ACPI), /* GPP_G6 - GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, RSMRST, OFF, ACPI), /* GPP_G7 - GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, RSMRST, OFF, ACPI), /* GPP_G8 - GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, RSMRST, OFF, ACPI), /* GPP_G9 - GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, RSMRST, OFF, ACPI), /* GPP_G10 - GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, RSMRST, OFF, ACPI), /* GPP_G11 - GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, RSMRST, OFF, ACPI), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, RSMRST, OFF, ACPI), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, RSMRST, OFF, ACPI), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, RSMRST, OFF, ACPI), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, RSMRST, OFF, ACPI), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI), /* GPP_G17 - ADR_COMPLETE */ - _PAD_CFG_STRUCT(GPP_G17, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ - _PAD_CFG_STRUCT(GPP_G18, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G19 - SMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI), /* GPP_G22 - n/a */ - _PAD_CFG_STRUCT(GPP_G22, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G22, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_G23 - GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H1 - GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ - _PAD_CFG_STRUCT(GPP_H6, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H6, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H8 - SRCCLKREQ14# */ - _PAD_CFG_STRUCT(GPP_H8, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H8, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ - _PAD_CFG_STRUCT(GPP_H12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, RSMRST, OFF, ACPI), /* GPP_H13 - RESERVED */ /* GPP_H14 - RESERVED */ /* GPP_H15 - GPIO */ - _PAD_CFG_STRUCT(GPP_H15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, RSMRST, OFF, ACPI), /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ /* GPP_H18 - GPIO */ - _PAD_CFG_STRUCT(GPP_H18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, RSMRST, OFF, ACPI), /* GPP_H19 - GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_H19, 0, RSMRST), /* GPP_H20 - SSATAXPCIE2 */ - _PAD_CFG_STRUCT(GPP_H20, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H20, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_H21 - GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_H21, 0, RSMRST), /* GPP_H22 - SSATAXPCIE4 */ - _PAD_CFG_STRUCT(GPP_H22, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H22, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_H23 - GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* GPP_L2 - TESTCH0_D0 */ - _PAD_CFG_STRUCT(GPP_L2, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L2, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L3 - TESTCH0_D1 */ - _PAD_CFG_STRUCT(GPP_L3, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L3, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L4 - TESTCH0_D2 */ - _PAD_CFG_STRUCT(GPP_L4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L5 - TESTCH0_D3 */ - _PAD_CFG_STRUCT(GPP_L5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L6 - TESTCH0_D4 */ - _PAD_CFG_STRUCT(GPP_L6, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L6, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L7 - TESTCH0_D5 */ - _PAD_CFG_STRUCT(GPP_L7, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L7, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L8 - TESTCH0_D6 */ - _PAD_CFG_STRUCT(GPP_L8, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L8, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L9 - TESTCH0_D7 */ - _PAD_CFG_STRUCT(GPP_L9, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L9, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L10 - TESTCH0_CLK */ - _PAD_CFG_STRUCT(GPP_L10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L11 - TESTCH1_D0 */ - _PAD_CFG_STRUCT(GPP_L11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L11, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L12 - TESTCH1_D1 */ - _PAD_CFG_STRUCT(GPP_L12, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L12, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L13 - TESTCH1_D2 */ - _PAD_CFG_STRUCT(GPP_L13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L14 - TESTCH1_D3 */ - _PAD_CFG_STRUCT(GPP_L14, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L14, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L15 - TESTCH1_D4 */ - _PAD_CFG_STRUCT(GPP_L15, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L15, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L16 - TESTCH1_D5 */ - _PAD_CFG_STRUCT(GPP_L16, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L16, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L17 - TESTCH1_D6 */ - _PAD_CFG_STRUCT(GPP_L17, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L17, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L18 - TESTCH1_D7 */ - _PAD_CFG_STRUCT(GPP_L18, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L18, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L19 - TESTCH1_CLK */ - _PAD_CFG_STRUCT(GPP_L19, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L19, NONE, RSMRST, NF1, RX_DISABLE, OFF), };
#endif /* CFG_PCH_GPIO_H */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 1:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 177: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 319: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 362: _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 366: _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 460: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 464: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 466: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 468: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 473: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/1/src/mainboard/intel/cedaris... PS1, Line 477: _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
Maxim Polyakov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
md/cedarisland_crb: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. However, the PAD_CFG_GPO_GPIO_DRIVER() macros are still used, since these macros were added to the project for a long time ago and some motherboards use them in the configuration. The issue related to these macros should be resolved in a separate patch.
[1] https: //review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 240 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40736/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 2:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 177: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 319: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 362: _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 366: _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 460: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 464: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 466: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 468: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 473: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/2/src/mainboard/intel/cedaris... PS2, Line 477: _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 3:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 177: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 319: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 362: _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 366: _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 460: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 464: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 466: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 468: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 473: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/3/src/mainboard/intel/cedaris... PS3, Line 477: _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
Maxim Polyakov has removed Andrey Petrov from this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Removed reviewer Andrey Petrov.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40736
to look at the new patch set (#4).
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
md/cedarisland_crb: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. However, the PAD_CFG_GPO_GPIO_DRIVER() macros are still used, since these macros were added to the project for a long time ago and some motherboards use them in the configuration. The issue related to these macros should be resolved in a separate patch.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 240 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40736/4
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40736
to look at the new patch set (#5).
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
md/cedarisland_crb: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 240 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40736/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 5:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 177: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 319: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 362: _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 366: _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 460: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 464: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 466: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 468: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 473: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 477: _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010), same here, I think we can skip a0-a7
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: PAD_CFG_NF_BUF_TRIG Most of the PAD_CFG_NF_BUF_TRIG can be replaced with PAD_CFG_NF, as long as BUF setting is don't care and trigger is all off.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010),
same here, I think we can skip a0-a7
See commets in CB:40731
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: PAD_CFG_NF_BUF_TRIG
Most of the PAD_CFG_NF_BUF_TRIG can be replaced with PAD_CFG_NF, as long as BUF setting is don't car […]
Unfortunately, we cannot use the PAD_CFG_NF() macro here because it sets the trig parameter to LEVEL (0 << 25):
https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/...
This is incorrect because the RXEVCFG field in the DW0 register is set to 2h (Drive '0') by default after a reset. The work to fix this error will take a lot of time, since all motherboards use this macro. Moreover, Google guys are very annoyed if someone changes all these macros :) For this reason, I added a new universal macro - PAD_CFG_NF_BUF_TRIG().
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: md/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 6:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 177: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 319: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 362: _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 366: _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 460: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 464: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 466: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 468: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 473: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/6/src/mainboard/intel/cedaris... PS6, Line 477: _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40736
to look at the new patch set (#7).
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
mb/cedarisland_crb: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 240 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40736/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 7:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 177: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 319: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 362: _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 366: _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 460: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 464: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 466: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 468: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 473: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/7/src/mainboard/intel/cedaris... PS7, Line 477: _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 7: Code-Review+2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010),
See commets in CB:40731
Ack
https://review.coreboot.org/c/coreboot/+/40736/5/src/mainboard/intel/cedaris... PS5, Line 14: PAD_CFG_NF_BUF_TRIG
Unfortunately, we cannot use the PAD_CFG_NF() macro here because it sets the trig parameter to LEVEL […]
Ack
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 8:
(10 comments)
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... File src/mainboard/intel/cedarisland_crb/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 177: _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 319: _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 362: _PAD_CFG_STRUCT(GPP_J13, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 366: _PAD_CFG_STRUCT(GPP_J15, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 460: _PAD_CFG_STRUCT(GPP_H0, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 464: _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 466: _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 468: _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 473: _PAD_CFG_STRUCT(GPP_H7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
https://review.coreboot.org/c/coreboot/+/40736/8/src/mainboard/intel/cedaris... PS8, Line 477: _PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), line over 96 characters
Hello build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40736
to look at the new patch set (#9).
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
mb/cedarisland_crb: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 270 insertions(+), 240 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40736/9
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 9: Code-Review+2
Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
mb/cedarisland_crb: rework GPIOs configuration using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736 Reviewed-by: Andrey Petrov andrey.petrov@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 270 insertions(+), 240 deletions(-)
Approvals: build bot (Jenkins): Verified Andrey Petrov: Looks good to me, approved
diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index 6aca58d..f9a9825 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -11,533 +11,563 @@ /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - ESPI_ALERT1# */ - _PAD_CFG_STRUCT(GPP_A0, 0x44000d02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF3, TX_DISABLE, OFF), /* GPP_A1 - ESPI_IO0 */ - _PAD_CFG_STRUCT(GPP_A1, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A2 - ESPI_IO1 */ - _PAD_CFG_STRUCT(GPP_A2, 0x44000c02, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A3 - ESPI_IO2 */ - _PAD_CFG_STRUCT(GPP_A3, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A4 - ESPI_IO3 */ - _PAD_CFG_STRUCT(GPP_A4, 0x44000c00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, DEEP, NF3, NO_DISABLE, OFF), /* GPP_A5 - ESPI_CS0# */ - _PAD_CFG_STRUCT(GPP_A5, 0x44000e00, 0x00003010), + PAD_CFG_NF_BUF_TRIG(GPP_A5, 20K_PU, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A6 - ESPI_CS1# */ - _PAD_CFG_STRUCT(GPP_A6, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A7 - ESPI_ALERT0# */ - _PAD_CFG_STRUCT(GPP_A7, 0x44000d02, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF3, TX_DISABLE, OFF), /* GPP_A8 - CLKRUN# */ - _PAD_CFG_STRUCT(GPP_A8, 0x44000400, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, NO_DISABLE, OFF), /* GPP_A9 - ESPI_CLK */ - _PAD_CFG_STRUCT(GPP_A9, 0x44000e00, 0x00001010), + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A10 - CLKOUT_LPC1 */ - _PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_DISABLE, OFF), /* GPP_A11 - GPIO */ - _PAD_CFG_STRUCT(GPP_A11, 0x44000102, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), /* GPP_A12 - GPIO */ - _PAD_CFG_STRUCT(GPP_A12, 0x80880102, 0x00000000), + PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), /* GPP_A13 - GPIO */ - _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x00000010), + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* GPP_A14 - ESPI_RESET# */ - _PAD_CFG_STRUCT(GPP_A14, 0x44000e00, 0x00000010), + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF3, RX_DISABLE, OFF), /* GPP_A15 - GPIO */ - _PAD_CFG_STRUCT(GPP_A15, 0x44000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), /* GPP_A16 - GPIO */ - _PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x00000010), + PAD_CFG_GPO(GPP_A16, 1, DEEP), /* GPP_A17 - GPIO */ - _PAD_CFG_STRUCT(GPP_A17, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, RSMRST, OFF, ACPI), /* GPP_A18 - GPIO */ - _PAD_CFG_STRUCT(GPP_A18, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, RSMRST, OFF, ACPI), /* GPP_A19 - RESERVED */ /* GPP_A20 - GPIO */ - _PAD_CFG_STRUCT(GPP_A20, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, RSMRST, OFF, ACPI), /* GPP_A21 - GPIO */ - _PAD_CFG_STRUCT(GPP_A21, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, RSMRST, OFF, ACPI), /* GPP_A22 - GPIO */ - _PAD_CFG_STRUCT(GPP_A22, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, RSMRST, OFF, ACPI), /* GPP_A23 - GPIO */ - _PAD_CFG_STRUCT(GPP_A23, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - _PAD_CFG_STRUCT(GPP_B0, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B1 - CORE_VID1 */ - _PAD_CFG_STRUCT(GPP_B1, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B2 - GPIO */ - _PAD_CFG_STRUCT(GPP_B2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI), /* GPP_B3 - GPIO */ - _PAD_CFG_STRUCT(GPP_B3, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, RSMRST, OFF, ACPI), /* GPP_B4 - GPIO */ - _PAD_CFG_STRUCT(GPP_B4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, RSMRST, OFF, ACPI), /* GPP_B5 - GPIO */ - _PAD_CFG_STRUCT(GPP_B5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, RSMRST, OFF, ACPI), /* GPP_B6 - GPIO */ - _PAD_CFG_STRUCT(GPP_B6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, RSMRST, OFF, ACPI), /* GPP_B7 - GPIO */ - _PAD_CFG_STRUCT(GPP_B7, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, RSMRST, OFF, ACPI), /* GPP_B8 - GPIO */ - _PAD_CFG_STRUCT(GPP_B8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, RSMRST, OFF, ACPI), /* GPP_B9 - GPIO */ - _PAD_CFG_STRUCT(GPP_B9, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, RSMRST, OFF, ACPI), /* GPP_B10 - GPIO */ - _PAD_CFG_STRUCT(GPP_B10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, RSMRST, OFF, ACPI), /* GPP_B11 - RESERVED */ /* GPP_B12 - GPIO */ - _PAD_CFG_STRUCT(GPP_B12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B12, NONE, RSMRST, OFF, ACPI), /* GPP_B13 - PLTRST# */ - _PAD_CFG_STRUCT(GPP_B13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_B14 - SPKR */ - _PAD_CFG_STRUCT(GPP_B14, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_B15 - GPIO */ - _PAD_CFG_STRUCT(GPP_B15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, RSMRST, OFF, ACPI), /* GPP_B16 - GPIO */ - _PAD_CFG_STRUCT(GPP_B16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, RSMRST, OFF, ACPI), /* GPP_B17 - GPIO */ - _PAD_CFG_STRUCT(GPP_B17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, RSMRST, OFF, ACPI), /* GPP_B18 - GPIO */ - _PAD_CFG_STRUCT(GPP_B18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, RSMRST, OFF, ACPI), /* GPP_B19 - GPIO */ - _PAD_CFG_STRUCT(GPP_B19, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, RSMRST, OFF, ACPI), /* GPP_B20 - GPIO */ - _PAD_CFG_STRUCT(GPP_B20, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_B20, 0, RSMRST), /* GPP_B21 - GPIO */ - _PAD_CFG_STRUCT(GPP_B21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, RSMRST, OFF, ACPI), /* GPP_B22 - GPIO */ - _PAD_CFG_STRUCT(GPP_B22, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPP_B23 - PCHHOT# */ - _PAD_CFG_STRUCT(GPP_B23, 0x04000a00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, OFF),
/* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - SATAXPCIE3 */ - _PAD_CFG_STRUCT(GPP_F0, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F0, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F1 - SATAXPCIE4 */ - _PAD_CFG_STRUCT(GPP_F1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F2 - SATAXPCIE5 */ - _PAD_CFG_STRUCT(GPP_F2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F3 - SATAXPCIE6 */ - _PAD_CFG_STRUCT(GPP_F3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F4 - SATAXPCIE7 */ - _PAD_CFG_STRUCT(GPP_F4, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F4, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPP_F6 - GPIO */ - _PAD_CFG_STRUCT(GPP_F6, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F6, 0, RSMRST), /* GPP_F7 - GPIO */ - _PAD_CFG_STRUCT(GPP_F7, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* GPP_F8 - GPIO */ - _PAD_CFG_STRUCT(GPP_F8, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_F8, 0, RSMRST), /* GPP_F9 - GPIO */ - _PAD_CFG_STRUCT(GPP_F9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI), /* GPP_F10 - SATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F11 - SATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F12 - SATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_F12, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F13 - SATA_SDATAOUT2 */ - _PAD_CFG_STRUCT(GPP_F13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_F14 - SSATA_LED# */ - _PAD_CFG_STRUCT(GPP_F14, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_F15 - USB_OC4# */ - _PAD_CFG_STRUCT(GPP_F15, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F16 - USB_OC5# */ - _PAD_CFG_STRUCT(GPP_F16, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F17 - USB_OC6# */ - _PAD_CFG_STRUCT(GPP_F17, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F18 - USB_OC7# */ - _PAD_CFG_STRUCT(GPP_F18, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F18, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_F19 - LAN_SMBCLK */ - _PAD_CFG_STRUCT(GPP_F19, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_F20 - LAN_SMBDATA */ - _PAD_CFG_STRUCT(GPP_F20, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_F21 - GPIO */ - _PAD_CFG_STRUCT(GPP_F21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, RSMRST, OFF, ACPI), /* GPP_F22 - SSATA_SCLOCK */ - _PAD_CFG_STRUCT(GPP_F22, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_F23 - SSATA_SLOAD */ - _PAD_CFG_STRUCT(GPP_F23, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, RSMRST, NF3, RX_DISABLE, OFF),
/* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - GPIO */ - _PAD_CFG_STRUCT(GPP_C2, 0x00000102, 0x00000000), + PAD_CFG_GPI(GPP_C2, NONE, RSMRST), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - SML0ALERT# */ - _PAD_CFG_STRUCT(GPP_C5, 0x04000602, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_C5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ /* GPP_C8 - GPIO */ - _PAD_CFG_STRUCT(GPP_C8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, RSMRST, OFF, ACPI), /* GPP_C9 - GPIO */ - _PAD_CFG_STRUCT(GPP_C9, 0x04000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, DRIVER), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_C10, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_C11 - GPIO */ - _PAD_CFG_STRUCT(GPP_C11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, RSMRST, OFF, ACPI), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, RSMRST, OFF, ACPI), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, RSMRST, OFF, ACPI), /* GPP_C14 - GPIO */ - _PAD_CFG_STRUCT(GPP_C14, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, RSMRST, OFF, ACPI), /* GPP_C15 - GPIO */ - _PAD_CFG_STRUCT(GPP_C15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, RSMRST, OFF, ACPI), /* GPP_C16 - GPIO */ - _PAD_CFG_STRUCT(GPP_C16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, RSMRST, OFF, ACPI), /* GPP_C17 - GPIO */ - _PAD_CFG_STRUCT(GPP_C17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, RSMRST, OFF, ACPI), /* GPP_C18 - GPIO */ - _PAD_CFG_STRUCT(GPP_C18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, RSMRST, OFF, ACPI), /* GPP_C19 - GPIO */ - _PAD_CFG_STRUCT(GPP_C19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_C19, 0, RSMRST), /* GPP_C20 - RESERVED */ /* GPP_C21 - GPIO */ - _PAD_CFG_STRUCT(GPP_C21, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_C21, 0, RSMRST), /* GPP_C22 - GPIO */ - _PAD_CFG_STRUCT(GPP_C22, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, RSMRST, OFF, ACPI), /* GPP_C23 - GPIO */ - _PAD_CFG_STRUCT(GPP_C23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - _PAD_CFG_STRUCT(GPP_D0, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, RSMRST, OFF, ACPI), /* GPP_D1 - GPIO */ - _PAD_CFG_STRUCT(GPP_D1, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D1, 0, RSMRST), /* GPP_D2 - GPIO */ - _PAD_CFG_STRUCT(GPP_D2, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D2, 0, RSMRST), /* GPP_D3 - GPIO */ - _PAD_CFG_STRUCT(GPP_D3, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, RSMRST, OFF, ACPI), /* GPP_D4 - GPIO */ - _PAD_CFG_STRUCT(GPP_D4, 0x04000201, 0x00000000), + PAD_CFG_GPO(GPP_D4, 1, RSMRST), /* GPP_D5 - GPIO */ - _PAD_CFG_STRUCT(GPP_D5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, RSMRST, OFF, ACPI), /* GPP_D6 - GPIO */ - _PAD_CFG_STRUCT(GPP_D6, 0x04000100, 0x00000010), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, DRIVER), /* GPP_D7 - GPIO */ - _PAD_CFG_STRUCT(GPP_D7, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI), /* GPP_D8 - GPIO */ - _PAD_CFG_STRUCT(GPP_D8, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, RSMRST, OFF, ACPI), /* GPP_D9 - GPIO */ - _PAD_CFG_STRUCT(GPP_D9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI), /* GPP_D10 - SSATA_DEVSLP4 */ - _PAD_CFG_STRUCT(GPP_D10, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D10, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D11 - GPIO */ - _PAD_CFG_STRUCT(GPP_D11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, RSMRST, OFF, ACPI), /* GPP_D12 - SSATA_SDATAOUT1 */ - _PAD_CFG_STRUCT(GPP_D12, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D12, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D13 - SML0BCLK_IE */ - _PAD_CFG_STRUCT(GPP_D13, 0x04000c02, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D13, NONE, RSMRST, NF3, NO_DISABLE, OFF), /* GPP_D14 - SML0BDATA_IE */ - _PAD_CFG_STRUCT(GPP_D14, 0x04000c02, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D14, NONE, RSMRST, NF3, NO_DISABLE, OFF), /* GPP_D15 - SSATA_SDATAOUT0 */ - _PAD_CFG_STRUCT(GPP_D15, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_D16 - GPIO */ - _PAD_CFG_STRUCT(GPP_D16, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPP_D17 - GPIO */ - _PAD_CFG_STRUCT(GPP_D17, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D17, 0, RSMRST), /* GPP_D18 - GPIO */ - _PAD_CFG_STRUCT(GPP_D18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, RSMRST, OFF, ACPI), /* GPP_D19 - GPIO */ - _PAD_CFG_STRUCT(GPP_D19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_D19, 0, RSMRST), /* GPP_D20 - GPIO */ - _PAD_CFG_STRUCT(GPP_D20, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, RSMRST, OFF, ACPI), /* GPP_D21 - GPIO */ - _PAD_CFG_STRUCT(GPP_D21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, RSMRST, OFF, ACPI), /* GPP_D22 - GPIO */ - _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), /* GPP_D23 - GPIO */ - _PAD_CFG_STRUCT(GPP_D23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - _PAD_CFG_STRUCT(GPP_E0, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E1 - SATAXPCIE1 */ - _PAD_CFG_STRUCT(GPP_E1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E2 - SATAXPCIE2 */ - _PAD_CFG_STRUCT(GPP_E2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E3 - CPU_GP0 */ - _PAD_CFG_STRUCT(GPP_E3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E4 - GPIO */ - _PAD_CFG_STRUCT(GPP_E4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, RSMRST, OFF, ACPI), /* GPP_E5 - GPIO */ - _PAD_CFG_STRUCT(GPP_E5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, RSMRST, OFF, ACPI), /* GPP_E6 - GPIO */ - _PAD_CFG_STRUCT(GPP_E6, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, RSMRST, OFF, ACPI), /* GPP_E7 - GPIO */ - _PAD_CFG_STRUCT(GPP_E7, 0x40840102, 0x00000000), + PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT), /* GPP_E8 - SATA_LED# */ - _PAD_CFG_STRUCT(GPP_E8, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_E9 - USB_OC0# */ - _PAD_CFG_STRUCT(GPP_E9, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E10 - USB_OC1# */ - _PAD_CFG_STRUCT(GPP_E10, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E11 - USB_OC2# */ - _PAD_CFG_STRUCT(GPP_E11, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_E12 - USB_OC3# */ - _PAD_CFG_STRUCT(GPP_E12, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, RSMRST, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 2 ------- */ /* -------- GPIO Group GPD -------- */ /* GPD0 - RESERVED */ /* GPD1 - ACPRESENT */ - _PAD_CFG_STRUCT(GPD1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD2 - GBE_WAKE# */ - _PAD_CFG_STRUCT(GPD2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD3 - PWRBTN# */ - _PAD_CFG_STRUCT(GPD3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPD4 - SLP_S3# */ - _PAD_CFG_STRUCT(GPD4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD5 - SLP_S4# */ - _PAD_CFG_STRUCT(GPD5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD6 - SLP_A# */ - _PAD_CFG_STRUCT(GPD6, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD6, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ - _PAD_CFG_STRUCT(GPD8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ - _PAD_CFG_STRUCT(GPD9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), /* GPD10 - SLP_S5# */ - _PAD_CFG_STRUCT(GPD10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPD11 - GBEPHY */ - _PAD_CFG_STRUCT(GPD11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, RX_DISABLE, OFF),
/* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - _PAD_CFG_STRUCT(GPP_I0, 0x04000a00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, RSMRST, NF2, RX_DISABLE, OFF), /* GPP_I1 - LAN_TCK */ - _PAD_CFG_STRUCT(GPP_I1, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I2 - LAN_TMS */ - _PAD_CFG_STRUCT(GPP_I2, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I3 - LAN_TDI */ - _PAD_CFG_STRUCT(GPP_I3, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_I4, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_I5 - GPIO */ - _PAD_CFG_STRUCT(GPP_I5, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_I5, 0, RSMRST), /* GPP_I6 - GPIO */ - _PAD_CFG_STRUCT(GPP_I6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI), /* GPP_I7 - LAN_TRST_IN */ - _PAD_CFG_STRUCT(GPP_I7, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I8 - PCI_DIS */ - _PAD_CFG_STRUCT(GPP_I8, 0x04000900, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I9 - LAN_DIS */ - _PAD_CFG_STRUCT(GPP_I9, 0x04000900, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_I10 - GPIO */ - _PAD_CFG_STRUCT(GPP_I10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - GPIO */ - _PAD_CFG_STRUCT(GPP_J0, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J0, 0, RSMRST), /* GPP_J1 - GPIO */ - _PAD_CFG_STRUCT(GPP_J1, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J1, 0, RSMRST), /* GPP_J2 - GPIO */ - _PAD_CFG_STRUCT(GPP_J2, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J2, 0, RSMRST), /* GPP_J3 - GPIO */ - _PAD_CFG_STRUCT(GPP_J3, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J3, 0, RSMRST), /* GPP_J4 - GPIO */ - _PAD_CFG_STRUCT(GPP_J4, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J4, 0, RSMRST), /* GPP_J5 - GPIO */ - _PAD_CFG_STRUCT(GPP_J5, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J5, 0, RSMRST), /* GPP_J6 - GPIO */ - _PAD_CFG_STRUCT(GPP_J6, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J6, 0, RSMRST), /* GPP_J7 - GPIO */ - _PAD_CFG_STRUCT(GPP_J7, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J7, 0, RSMRST), /* GPP_J8 - GPIO */ - _PAD_CFG_STRUCT(GPP_J8, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J8, 0, RSMRST), /* GPP_J9 - GPIO */ - _PAD_CFG_STRUCT(GPP_J9, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J9, 0, RSMRST), /* GPP_J10 - GPIO */ - _PAD_CFG_STRUCT(GPP_J10, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J10, 0, RSMRST), /* GPP_J11 - GPIO */ - _PAD_CFG_STRUCT(GPP_J11, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J11, 0, RSMRST), /* GPP_J12 - GPIO */ - _PAD_CFG_STRUCT(GPP_J12, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J12, 0, RSMRST), /* GPP_J13 - GPIO */ - _PAD_CFG_STRUCT(GPP_J13, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_J13, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_J14 - GPIO */ - _PAD_CFG_STRUCT(GPP_J14, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J14, 0, RSMRST), /* GPP_J15 - GPIO */ - _PAD_CFG_STRUCT(GPP_J15, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_J15, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_J16 - GPIO */ - _PAD_CFG_STRUCT(GPP_J16, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J16, 0, RSMRST), /* GPP_J17 - GPIO */ - _PAD_CFG_STRUCT(GPP_J17, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, RSMRST, OFF, ACPI), /* GPP_J18 - GPIO */ - _PAD_CFG_STRUCT(GPP_J18, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J18, 0, RSMRST), /* GPP_J19 - GPIO */ - _PAD_CFG_STRUCT(GPP_J19, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, RSMRST, OFF, ACPI), /* GPP_J20 - GPIO */ - _PAD_CFG_STRUCT(GPP_J20, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J20, 0, RSMRST), /* GPP_J21 - GPIO */ - _PAD_CFG_STRUCT(GPP_J21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, RSMRST, OFF, ACPI), /* GPP_J22 - GPIO */ - _PAD_CFG_STRUCT(GPP_J22, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_J22, 0, RSMRST), /* GPP_J23 - GPIO */ - _PAD_CFG_STRUCT(GPP_J23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_K ------- */ /* GPP_K0 - LAN_NCSI_CLK_IN */ - _PAD_CFG_STRUCT(GPP_K0, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K0, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_K1 - LAN_NCSI_TXD0 */ - _PAD_CFG_STRUCT(GPP_K1, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K1, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K2 - LAN_NCSI_TXD1 */ - _PAD_CFG_STRUCT(GPP_K2, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K2, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K3 - LAN_NCSI_TX_EN */ - _PAD_CFG_STRUCT(GPP_K3, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K3, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K4 - LAN_NCSI_CRS_DV */ - _PAD_CFG_STRUCT(GPP_K4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_K5 - LAN_NCSI_RXD0 */ - _PAD_CFG_STRUCT(GPP_K5, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K5, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K6 - LAN_NCSI_RXD1 */ - _PAD_CFG_STRUCT(GPP_K6, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K6, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K7 - RESERVED */ - _PAD_CFG_STRUCT(GPP_K7, 0x04000402, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, RSMRST, NF1, NO_DISABLE, OFF), /* GPP_K8 - LAN_NCSI_ARB_IN */ - _PAD_CFG_STRUCT(GPP_K8, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - _PAD_CFG_STRUCT(GPP_K9, 0x04000602, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_K10 - PE_RST# */ - _PAD_CFG_STRUCT(GPP_K10, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, RSMRST, NF1, TX_DISABLE, OFF),
/* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - _PAD_CFG_STRUCT(GPP_G0, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, RSMRST, OFF, ACPI), /* GPP_G1 - GPIO */ - _PAD_CFG_STRUCT(GPP_G1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, RSMRST, OFF, ACPI), /* GPP_G2 - GPIO */ - _PAD_CFG_STRUCT(GPP_G2, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, RSMRST, OFF, ACPI), /* GPP_G3 - GPIO */ - _PAD_CFG_STRUCT(GPP_G3, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, RSMRST, OFF, ACPI), /* GPP_G4 - GPIO */ - _PAD_CFG_STRUCT(GPP_G4, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, RSMRST, OFF, ACPI), /* GPP_G5 - GPIO */ - _PAD_CFG_STRUCT(GPP_G5, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, RSMRST, OFF, ACPI), /* GPP_G6 - GPIO */ - _PAD_CFG_STRUCT(GPP_G6, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, RSMRST, OFF, ACPI), /* GPP_G7 - GPIO */ - _PAD_CFG_STRUCT(GPP_G7, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, RSMRST, OFF, ACPI), /* GPP_G8 - GPIO */ - _PAD_CFG_STRUCT(GPP_G8, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, RSMRST, OFF, ACPI), /* GPP_G9 - GPIO */ - _PAD_CFG_STRUCT(GPP_G9, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, RSMRST, OFF, ACPI), /* GPP_G10 - GPIO */ - _PAD_CFG_STRUCT(GPP_G10, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, RSMRST, OFF, ACPI), /* GPP_G11 - GPIO */ - _PAD_CFG_STRUCT(GPP_G11, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, RSMRST, OFF, ACPI), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, RSMRST, OFF, ACPI), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, RSMRST, OFF, ACPI), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, RSMRST, OFF, ACPI), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, 0x04000100, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, RSMRST, OFF, ACPI), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, RSMRST, OFF, ACPI), /* GPP_G17 - ADR_COMPLETE */ - _PAD_CFG_STRUCT(GPP_G17, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */ - _PAD_CFG_STRUCT(GPP_G18, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G19 - SMI# */ - _PAD_CFG_STRUCT(GPP_G19, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ - _PAD_CFG_STRUCT(GPP_G21, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, RSMRST, OFF, ACPI), /* GPP_G22 - n/a */ - _PAD_CFG_STRUCT(GPP_G22, 0x04000e00, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_G22, NONE, RSMRST, NF3, RX_DISABLE, OFF), /* GPP_G23 - GPIO */ - _PAD_CFG_STRUCT(GPP_G23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H0, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H1 - GPIO */ - _PAD_CFG_STRUCT(GPP_H1, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H2, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H3, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H4, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ - _PAD_CFG_STRUCT(GPP_H6, 0x04000502, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H6, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H7, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H8 - SRCCLKREQ14# */ - _PAD_CFG_STRUCT(GPP_H8, 0x04000500, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H8, NONE, RSMRST, NF1, TX_DISABLE, OFF), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, 0x04000000, 0x00000000), + _PAD_CFG_STRUCT(GPP_H9, + PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), + PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ - _PAD_CFG_STRUCT(GPP_H12, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, RSMRST, OFF, ACPI), /* GPP_H13 - RESERVED */ /* GPP_H14 - RESERVED */ /* GPP_H15 - GPIO */ - _PAD_CFG_STRUCT(GPP_H15, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, RSMRST, OFF, ACPI), /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ /* GPP_H18 - GPIO */ - _PAD_CFG_STRUCT(GPP_H18, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, RSMRST, OFF, ACPI), /* GPP_H19 - GPIO */ - _PAD_CFG_STRUCT(GPP_H19, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_H19, 0, RSMRST), /* GPP_H20 - SSATAXPCIE2 */ - _PAD_CFG_STRUCT(GPP_H20, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H20, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_H21 - GPIO */ - _PAD_CFG_STRUCT(GPP_H21, 0x04000200, 0x00000000), + PAD_CFG_GPO(GPP_H21, 0, RSMRST), /* GPP_H22 - SSATAXPCIE4 */ - _PAD_CFG_STRUCT(GPP_H22, 0x04000902, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_H22, NONE, RSMRST, NF2, TX_DISABLE, OFF), /* GPP_H23 - GPIO */ - _PAD_CFG_STRUCT(GPP_H23, 0x04000102, 0x00000000), + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, RSMRST, OFF, ACPI),
/* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - _PAD_CFG_STRUCT(GPP_L1, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* GPP_L2 - TESTCH0_D0 */ - _PAD_CFG_STRUCT(GPP_L2, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L2, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L3 - TESTCH0_D1 */ - _PAD_CFG_STRUCT(GPP_L3, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L3, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L4 - TESTCH0_D2 */ - _PAD_CFG_STRUCT(GPP_L4, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L4, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L5 - TESTCH0_D3 */ - _PAD_CFG_STRUCT(GPP_L5, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L5, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L6 - TESTCH0_D4 */ - _PAD_CFG_STRUCT(GPP_L6, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L6, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L7 - TESTCH0_D5 */ - _PAD_CFG_STRUCT(GPP_L7, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L7, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L8 - TESTCH0_D6 */ - _PAD_CFG_STRUCT(GPP_L8, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L8, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L9 - TESTCH0_D7 */ - _PAD_CFG_STRUCT(GPP_L9, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L9, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L10 - TESTCH0_CLK */ - _PAD_CFG_STRUCT(GPP_L10, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L10, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L11 - TESTCH1_D0 */ - _PAD_CFG_STRUCT(GPP_L11, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L11, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L12 - TESTCH1_D1 */ - _PAD_CFG_STRUCT(GPP_L12, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L12, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L13 - TESTCH1_D2 */ - _PAD_CFG_STRUCT(GPP_L13, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L13, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L14 - TESTCH1_D3 */ - _PAD_CFG_STRUCT(GPP_L14, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L14, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L15 - TESTCH1_D4 */ - _PAD_CFG_STRUCT(GPP_L15, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L15, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L16 - TESTCH1_D5 */ - _PAD_CFG_STRUCT(GPP_L16, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L16, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L17 - TESTCH1_D6 */ - _PAD_CFG_STRUCT(GPP_L17, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L17, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L18 - TESTCH1_D7 */ - _PAD_CFG_STRUCT(GPP_L18, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L18, NONE, RSMRST, NF1, RX_DISABLE, OFF), /* GPP_L19 - TESTCH1_CLK */ - _PAD_CFG_STRUCT(GPP_L19, 0x04000600, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_L19, NONE, RSMRST, NF1, RX_DISABLE, OFF), };
#endif /* CFG_PCH_GPIO_H */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40736 )
Change subject: mb/cedarisland_crb: rework GPIOs configuration using macros ......................................................................
Patch Set 10:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2976 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2975 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2974 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2973
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Andrey Petrov (Code Review)
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build bot (Jenkins) (Code Review)
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Lance Zhao (Code Review)
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Maxim Polyakov (Code Review)