Attention is currently required from: Wonkyu Kim, Paul Menzel, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 )
Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63615/comment/e5ddcdca_b9f9adaa PS4, Line 10: As there is no harm to enable : MCHBAR from bootblock even in existing plaforms
Enabling MCHBAR takes a PCI config register write or two, so size isn't a concern. The main reason is that the GPMR driver needs to access MCHBAR registers in bootblock code.
+1 to Angel's question. do we need to use GPMR access even in bootblock. Today with ADL and previous generation I don't see such usage.
Well, only MTL needs MCHBAR access to configure GPMR stuff, the registers are in DMI PCR space for older platforms. AFAIUI, the GPMR driver is needed to configure some decode ranges in bootblock, I think stuff like ACPIBASE, PMBASE, SMBUS TCOBASE, LPC I/O enable/decode, etc. could need the GPMR driver in bootblock.
There are two PMC IP, so I believe you are right, to configure PMC controller for IOC die, we need additional IOC driver.
Like to hear the new flow from Will in more details.
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Subrata Banik (Code Review)