New patch to review for coreboot: 89922a9 superio/nuvoton: Adds a function to route pins 41-48 to UARTD
Dave Frodin (dave.frodin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5963
-gerrit
commit 89922a940494c8f52823e27d32d22074b4ebf6b8 Author: Dave Frodin dave.frodin@se-eng.com Date: Mon Jun 9 12:33:24 2014 -0600
superio/nuvoton: Adds a function to route pins 41-48 to UARTD
Pins 41-48 default to being GPIs. This switches the internal mux to connect them to UARTD.
Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/superio/nuvoton/common/early_serial.c | 13 +++++++++++++ src/superio/nuvoton/common/nuvoton.h | 1 + 2 files changed, 14 insertions(+)
diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 1cbcee8..3c06929 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -73,3 +73,16 @@ void nuvoton_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); } + +/* Route UARTD to pin */ +void nuvoton_enable_uartd(device_t dev) +{ + u8 tmp; + u16 port = dev >> 8; + pnp_enter_conf_state(dev); + outb(0x1c, port); + tmp = inb(port + 1); + tmp |= 0x04; + outb(tmp, port + 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index e9e8d4b..440bad4 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -26,5 +26,6 @@ #include <stdint.h>
void nuvoton_enable_serial(device_t dev, u16 iobase); +void nuvoton_enable_uartd(device_t dev);
#endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */
-
Dave Frodin