Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition - coreboot-gerrit

12 May 2021


      Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held.
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54070 )
Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition
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Patch Set 2: Code-Review+1
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/54070/comment/79d93ae1_fdfdc5ae 
PS2, Line 522: 	espi_write32(ESPI_SLAVE0_INT_STS,
Can this just be espi_clear_status() or espi_write(ESPI_SLAVE0_INT_STS, status)?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I71271377f20eaf29032214be98794e1645d9b70a
Gerrit-Change-Number: 54070
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