Change in coreboot[master]: soc/intel/jsl: Control Fivr bypass mode by DisableExternalVnnVcc1p05B...
Attention is currently required from: Paul Menzel. Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55744 )
Change subject: soc/intel/jsl: Control Fivr bypass mode by DisableExternalVnnVcc1p05BypassMode config ......................................................................
Patch Set 9:
(6 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/55744/comment/d3b204c1_c7b5f29f PS7, Line 8:
Please elaborate, what the problem is.
Done
Patchset:
PS9: Hi Paul,
Sorry for the mistakes, I just push wrong changes to review. Thanks to your kindly reminding.
I just made a new change to correct them, if you have time please correct me if anything still not perfect one.
BTW, I am also changing the config name after discussed internally.
Simon
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/55744/comment/2f56b517_c15d99be PS7, Line 23: #define MAX_HD_AUDIO_SSP_LINKS 6
Please revert this (unrelated) hunk.
Done
https://review.coreboot.org/c/coreboot/+/55744/comment/ff62e38e_1ff573ab PS7, Line 408: do
does
Done
File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55744/comment/c6e6e6f7_a0358df2 PS7, Line 69: params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
Unrelated.
Done
https://review.coreboot.org/c/coreboot/+/55744/comment/d55899c8_8118f315 PS7, Line 186: config->PchPmSlpAMinAssert, config->PchPmPwrCycDur);
Unrelated.
Done
-
Simon Yang (Code Review)