Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3008
-gerrit
commit 3fe48146cd3dd8a2e2f1010e39cd682d3e79ddc3 Author: Aaron Durbin adurbin@chromium.org Date: Mon Apr 1 16:49:31 2013 -0500
haswell: keep ROM cache enabled
The MP code on haswell was mirroring the BSPs MTRRs. In addition it was cleaning up the ROM cache so that the MTRR register values were the same once the OS was booted. Since the hyperthread sibling of the BSP was going through this path the ROM cache was getting torn down once the hyperthread was brought up.
That said, there was no differnce in observed boot time keeping the ROM cache enabled.
Change-Id: I2a59988fcfeea9291202c961636ea761c2538837 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/cpu/intel/haswell/mp_init.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index cc13892..ddcff6c 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -181,8 +181,12 @@ ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr);
- /* Cleanup ROM caching. */ - cleanup_rom_caching(); + /* The MTRR resources are core scoped. Therefore, there is no need + * to do the same work twice. Additionally, this check keeps the + * ROM cache enabled on the BSP since its hyperthread sibling won't + * call cleanup_rom_caching(). */ + if ((lapicid() & 1) == 0) + cleanup_rom_caching();
/* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */
-
Aaron Durbin