Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30858
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
mb/google/sarien: Enable Camarillo Device
Whiskeylake processor have an internal devices called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded.
BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30858/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cccddce..a532cae 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -33,6 +33,7 @@ register "dptf_enable" = "1" register "dmipwroptimize" = "1" register "satapwroptimize" = "1" + register "Device4Enable" = "1"
# Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b590bac..dd6f251 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -42,6 +42,7 @@ register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "2" register "SlowSlewRateForFivr" = "2" + register "Device4Enable" = "1"
# Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30858/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30858/1//COMMIT_MSG@9 PS1, Line 9: devices device
Hello Pratikkumar V Prajapati, Sumeet R Pawnikar, Subrata Banik, Bora Guvendik, Hannah Williams, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30858
to look at the new patch set (#2).
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
mb/google/sarien: Enable Camarillo Device
Whiskeylake processor have an internal device called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded.
BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30858/2
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30858/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30858/1//COMMIT_MSG@9 PS1, Line 9: devices
device
Done
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
Patch Set 2: Code-Review+2
I have tested and verified this change on Arcada/Sarien system and works fine.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
Patch Set 2: Code-Review+2
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
Patch Set 2:
Please, help to merge this. Thanks.
Patrick Georgi has uploaded a new patch set (#3) to the change originally created by Lijian Zhao. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
mb/google/sarien: Enable Camarillo Device
Whiskeylake processor have an internal device called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded.
BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30858/3
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
Patch Set 3: Code-Review+2
trivial, yet manual rebase. inherit older CR+2.
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30858 )
Change subject: mb/google/sarien: Enable Camarillo Device ......................................................................
mb/google/sarien: Enable Camarillo Device
Whiskeylake processor have an internal device called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded.
BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen.
Signed-off-by: Lijian Zhao lijian.zhao@intel.com Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 Reviewed-on: https://review.coreboot.org/c/30858 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index fa926ae..ff26cbf 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -35,6 +35,7 @@ register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" + register "Device4Enable" = "1"
# Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 48404a8..37ef3dc5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -44,6 +44,7 @@ register "SlowSlewRateForFivr" = "2" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" + register "Device4Enable" = "1"
# Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
-
Angel Pons (Code Review) -
Duncan Laurie (Code Review)
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Lijian Zhao (Code Review)
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Patrick Georgi (Code Review)
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Pratikkumar V Prajapati (Code Review)
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Sumeet R Pawnikar (Code Review)