Patch set updated for coreboot: 4025b3e rambi: Enable internal keyboard

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4915

-gerrit

commit 4025b3e5a85a79309f04c2fa917683c6035a03cb
Author: Duncan Laurie 
Date:   Thu Oct 31 10:10:20 2013 -0700

rambi: Enable internal keyboard

The EC LPC init function needs to run to enable the internal keyboard.

I needed this to confirm that it is just USB keyboards that are causing
    all sorts of issues.

BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=boot to recovery screen and hit tab

Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
    Signed-off-by: Duncan Laurie 
    Reviewed-on: https://chromium-review.googlesource.com/175207
    Reviewed-by: Aaron Durbin 
    Signed-off-by: Aaron Durbin 
---
 src/mainboard/google/rambi/devicetree.cb | 10 +++++++++-
 src/soc/intel/baytrail/southcluster.c    |  2 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index e7f86ce..66d98ed 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -38,7 +38,15 @@ chip soc/intel/baytrail
    	device pci 1e.3 off end # HSUART1
    	device pci 1e.4 on  end # HSUART2
    	device pci 1e.5 on  end # SPI
-		device pci 1f.0 on  end # LPC Bridge
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				# We only have one init function that
+				# we need to call to initialize the
+				# keyboard part of the EC.
+				device pnp ff.1 on # dummy address
+				end
+			end
+		end # LPC Bridge
    	device pci 1f.3 off end # SMBus
    end
 end
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index b58f0e0..eacabf3 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -385,7 +385,7 @@ static struct device_operations device_ops = {
    .enable_resources	= NULL,
    .init			= NULL,
    .enable			= southcluster_enable_dev,
-	.scan_bus		= NULL,
+	.scan_bus		= scan_static_bus,
    .ops_pci		= &soc_pci_ops,
 };