Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27039
Change subject: [RFC]sb/intel/acpi_pirq_gen.c: Have the southbridge provide RCBA ......................................................................
[RFC]sb/intel/acpi_pirq_gen.c: Have the southbridge provide RCBA
Instead of redefining the RCBA macros, have the southbridge provide the offset.
Change-Id: I5beb7ffd460f32deaa9e0f397f444baeee9c41fb Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h 5 files changed, 11 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/27039/1
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 611b08f..10a0ffa 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -824,7 +824,7 @@ config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); - intel_acpi_gen_def_acpi_pirq(dev); + intel_acpi_gen_def_acpi_pirq(dev, (uint32_t *)DEFAULT_RCBA); }
static void lpc_final(struct device *dev) diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 1f1a2ab..2fbc395 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -27,7 +27,7 @@ EMIT_PICM, };
-static int create_pirq_matrix(char matrix[32][4]) +static int create_pirq_matrix(char matrix[32][4], const uint32_t *rcba) { struct device *dev; int num_devs = 0; @@ -45,7 +45,7 @@ continue;
matrix[pci_dev][int_pin - PCI_INT_A] = - intel_common_map_pirq(dev, int_pin); + intel_common_map_pirq(dev, int_pin, rcba); printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n", dev_path(dev), int_pin - PCI_INT_A, matrix[pci_dev][int_pin - PCI_INT_A] - PIRQ_A); @@ -84,7 +84,7 @@ } }
-void intel_acpi_gen_def_acpi_pirq(struct device *dev) +void intel_acpi_gen_def_acpi_pirq(struct device *dev, const uint32_t *rcba) { const char *lpcb_path = acpi_device_path(dev); char pci_int_mapping[32][4]; @@ -98,7 +98,7 @@ }
memset(pci_int_mapping, 0, sizeof(pci_int_mapping)); - num_devs = create_pirq_matrix(pci_int_mapping); + num_devs = create_pirq_matrix(pci_int_mapping, rcba);
acpigen_write_scope("\_SB.PCI0"); acpigen_write_method("_PRT", 0); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h index 9fdee1a..39549c0 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.h +++ b/src/southbridge/intel/common/acpi_pirq_gen.h @@ -36,8 +36,9 @@ PIRQ_H, };
-void intel_acpi_gen_def_acpi_pirq(struct device *dev); +void intel_acpi_gen_def_acpi_pirq(struct device *dev, const uint32_t *rcba); enum pirq intel_common_map_pirq(const struct device *dev, - const enum pci_pin pci_pin); + const enum pci_pin pci_pin, + const uint32_t *rcba);
#endif diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 7f97971..f1e4a82 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -28,7 +28,8 @@ };
enum pirq intel_common_map_pirq(const struct device *dev, - const enum pci_pin pci_pin) + const enum pci_pin pci_pin, + const uint32_t *rcba) { u8 slot = PCI_SLOT(dev->path.pci.devfn); u8 shift = 4 * (pci_pin - PCI_INT_A); @@ -50,7 +51,7 @@
reg = pirq_dir_route_reg[slot - MIN_SLOT];
- pirq = (RCBA16(reg) >> shift) & 0x7; + pirq = (read16(rcba + reg) >> shift) & 0x7;
return (enum pirq)(PIRQ_A + pirq); } diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h index cf76fb3..e5ac409 100644 --- a/src/southbridge/intel/common/rcba_pirq.h +++ b/src/southbridge/intel/common/rcba_pirq.h @@ -37,8 +37,4 @@ #define D20IR 0x3160 /* 16bit */ #define D19IR 0x3168 /* 16bit */
-#define DEFAULT_RCBA 0xfed1c000 - -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) - #endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */