Change in ...coreboot[master]: Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in R...

[Daniel Kurtz (Code Review)]

Hello Daniel Kurtz,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/30997

to review the following change.

Change subject: Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"
......................................................................

Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"

This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b.

Reason for revert:
It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config,
not its SCI configuration.

Signed-off-by: Daniel Kurtz

BUG=b:113880780
BRANCH=none
TEST=Boot grunt, does not go to recovery screen

Change-Id: I500934f3e03e66c97873accd4a979a23d4509675
---
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
1 file changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/30997/1

diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 399c78c..e9ae28c 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -117,9 +117,6 @@
    /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */
    PAD_GPI(GPIO_8, PULL_UP),

-	/* GPIO_9 - H1_PCH_INT_ODL, SCI */
-	PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW),
-
    /* GPIO_10 - SLP_S0_L (currently not used) */
    PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30997 )

Change subject: Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"
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Patch Set 1: Code-Review+2

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30997 )

Change subject: Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"
......................................................................

Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"

This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b.

Reason for revert:
It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config,
not its SCI configuration.

Signed-off-by: Daniel Kurtz

BUG=b:113880780
BRANCH=none
TEST=Boot grunt, does not go to recovery screen

Change-Id: I500934f3e03e66c97873accd4a979a23d4509675
Reviewed-on: https://review.coreboot.org/c/30997
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
1 file changed, 0 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 399c78c..e9ae28c 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -117,9 +117,6 @@
    /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */
    PAD_GPI(GPIO_8, PULL_UP),

-	/* GPIO_9 - H1_PCH_INT_ODL, SCI */
-	PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW),
-
    /* GPIO_10 - SLP_S0_L (currently not used) */
    PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),