Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42435 )
Change subject: superio/nuvoton/nct6779d: Add HWM API ......................................................................
superio/nuvoton/nct6779d: Add HWM API
Still testing on Asus P8Z77-V LX2.
Change-Id: I6ddf963638787b6c0041e198576c791618247e9f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p8z77-v_lx2/Kconfig M src/mainboard/asus/p8z77-v_lx2/early_init.c M src/superio/nuvoton/nct6779d/Kconfig M src/superio/nuvoton/nct6779d/Makefile.inc A src/superio/nuvoton/nct6779d/nct6779d_hwm.c A src/superio/nuvoton/nct6779d/nct6779d_hwm.h 6 files changed, 299 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42435/1
diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig index 4e96c59..357b399 100644 --- a/src/mainboard/asus/p8z77-v_lx2/Kconfig +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig @@ -14,6 +14,7 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_NUVOTON_NCT6779D + select SUPERIO_NUVOTON_NCT6779D_HWM select USE_NATIVE_RAMINIT
config MAINBOARD_DIR diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c index ecfb542..3b6b576 100644 --- a/src/mainboard/asus/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8z77-v_lx2/early_init.c @@ -7,10 +7,14 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> +#include <superio/nuvoton/nct6779d/nct6779d_hwm.h>
#define GLOBAL_DEV PNP_DEV(0x2e, 0) #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define HWM_DEV PNP_DEV(0x2e, NCT6779D_HWM_FPLED) + +#define HWM_BASE 0x290
const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, @@ -48,6 +52,47 @@
nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+ /* Set up the HWM */ + nct6779d_hwm_init(HWM_DEV, HWM_BASE); + + nct6779d_hwm_force_fan_full_on(HWM_BASE, SYS_FAN); + nct6779d_hwm_force_fan_full_on(HWM_BASE, CPU_FAN); + nct6779d_hwm_force_fan_full_on(HWM_BASE, AUX_FAN0); + nct6779d_hwm_force_fan_full_on(HWM_BASE, AUX_FAN1); + nct6779d_hwm_force_fan_full_on(HWM_BASE, AUX_FAN2); + + nct6779d_hwm_enable_peci(HWM_BASE); + + struct nct6779d_hwm_thermal_cruise_params tcp = { + .target_temp = 55, + .tolerance = 0, + .start_up_val = 1, + .stop_val = 0, + .stopduty_en = false, + .stop_time = 1, + .step_up_time = 1, + .step_down_time = 1, + .critical_temp = 60, + .temp_src = PECI_0, + }; + + nct6779d_hwm_program_thermal_cruise(HWM_BASE, SYS_FAN, &tcp); + nct6779d_hwm_program_thermal_cruise(HWM_BASE, CPU_FAN, &tcp); + nct6779d_hwm_program_thermal_cruise(HWM_BASE, AUX_FAN0, &tcp); + nct6779d_hwm_program_thermal_cruise(HWM_BASE, AUX_FAN1, &tcp); + nct6779d_hwm_program_thermal_cruise(HWM_BASE, AUX_FAN2, &tcp); + +#if 0 + struct nct6779d_hwm_speed_cruise_params scp = { + .target_speed = 4095, + .tolerance = 0, + .step_up_time = 1, + .step_down_time = 1, + }; + + nct6779d_hwm_program_speed_cruise(HWM_BASE, CPU_FAN, &scp); +#endif + /* Enable UART */ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/superio/nuvoton/nct6779d/Kconfig b/src/superio/nuvoton/nct6779d/Kconfig index ce2af16..9844c99 100644 --- a/src/superio/nuvoton/nct6779d/Kconfig +++ b/src/superio/nuvoton/nct6779d/Kconfig @@ -3,3 +3,9 @@ config SUPERIO_NUVOTON_NCT6779D bool select SUPERIO_NUVOTON_COMMON_PRE_RAM + +config SUPERIO_NUVOTON_NCT6779D_HWM + bool + depends on SUPERIO_NUVOTON_NCT6779D + select SUPERIO_NUVOTON_COMMON_HWM + default n diff --git a/src/superio/nuvoton/nct6779d/Makefile.inc b/src/superio/nuvoton/nct6779d/Makefile.inc index d5476e4..286be06 100644 --- a/src/superio/nuvoton/nct6779d/Makefile.inc +++ b/src/superio/nuvoton/nct6779d/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later
ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c + +all-$(CONFIG_SUPERIO_NUVOTON_NCT6779D_HWM) += nct6779d_hwm.c diff --git a/src/superio/nuvoton/nct6779d/nct6779d_hwm.c b/src/superio/nuvoton/nct6779d/nct6779d_hwm.c new file mode 100644 index 0000000..f43f1aa --- /dev/null +++ b/src/superio/nuvoton/nct6779d/nct6779d_hwm.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <device/pnp_type.h> +#include <device/pnp_ops.h> +#include <superio/conf_mode.h> +#include <superio/hwm5_conf.h> +#include <superio/nuvoton/common/hwm.h> +#include <superio/nuvoton/common/nuvoton.h> + +#include "nct6779d_hwm.h" +#include "nct6779d.h" + +#if ENV_PNP_SIMPLE_DEVICE +void nct6779d_hwm_init(pnp_devfn_t dev, const u16 base) +{ + nuvoton_pnp_enter_conf_state(dev); + + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, 0x60, base); + + nuvoton_pnp_exit_conf_state(dev); +} +#endif + +/* Higher order fan control functions */ +void nct6779d_hwm_force_fan_full_on( + const u16 base, + const enum nct6779d_hwm_fan fan) +{ + nct6779d_hwm_set_fan_mode(base, fan, FAN_MODE_MANUAL); + nct6779d_hwm_set_fan_duty(base, fan, 0xff); +} + +void nct6779d_hwm_program_thermal_cruise( + const u16 base, + const enum nct6779d_hwm_fan fan, + const struct nct6779d_hwm_thermal_cruise_params *const tcp) +{ + /* For safety reasons, disengage fan control before reconfiguring this output */ + nct6779d_hwm_force_fan_full_on(base, fan); + + /* High bits of stop duty enable and temperature source go into the same register */ + const u8 temp = (((!!tcp->stopduty_en) << 7) & 0x80) | (tcp->temp_src & 0x0f); + + /* Now, program Thermal Cruise mode using the desired settings */ + pnp_unset_and_set_hwm5_index(base, 0x00, 0x8f, temp); + pnp_unset_and_set_hwm5_index(base, 0x02, 0x07, tcp->tolerance); + + pnp_write_hwm5_index(base, 0x01, tcp->target_temp); + pnp_write_hwm5_index(base, 0x06, tcp->start_up_val); + pnp_write_hwm5_index(base, 0x05, tcp->stop_val); + pnp_write_hwm5_index(base, 0x07, tcp->stop_time); + pnp_write_hwm5_index(base, 0x03, tcp->step_up_time); + pnp_write_hwm5_index(base, 0x04, tcp->step_down_time); + pnp_write_hwm5_index(base, 0x35, tcp->critical_temp); + + /* Set fan speed to midpoint */ + nct6779d_hwm_set_fan_duty(base, fan, 0x7f); + + /* And enable Thermal Cruise mode */ + nct6779d_hwm_set_fan_mode(base, fan, FAN_MODE_THERMAL_CRUISE); +} + +void nct6779d_hwm_program_speed_cruise( + const u16 base, + const enum nct6779d_hwm_fan fan, + const struct nct6779d_hwm_speed_cruise_params *const scp) +{ + /* For safety reasons, disengage fan control before reconfiguring this output */ + nct6779d_hwm_force_fan_full_on(base, fan); + + /* High bits of target speed and tolerance go into the same register */ + const u8 temp = ((scp->tolerance << 1) & 0x70) | ((scp->target_speed >> 8) & 0x0f); + + /* Now, program Speed Cruise mode using the desired settings */ + pnp_unset_and_set_hwm5_index(base, 0x0c, 0x7f, temp); + pnp_unset_and_set_hwm5_index(base, 0x02, 0x07, scp->tolerance); + + pnp_write_hwm5_index(base, 0x01, (u8)scp->target_speed); + pnp_write_hwm5_index(base, 0x03, scp->step_up_time); + pnp_write_hwm5_index(base, 0x04, scp->step_down_time); + + /* Set fan speed to midpoint */ + nct6779d_hwm_set_fan_duty(base, fan, 0x7f); + + /* And enable Thermal Cruise mode */ + nct6779d_hwm_set_fan_mode(base, fan, FAN_MODE_SPEED_CRUISE); +} + +void nct6779d_hwm_enable_peci(const u16 base) +{ + nuvoton_hwm_select_bank(base, 0); + pnp_unset_and_set_hwm5_index(base, 0xae, 0x03, 0x01); + + nuvoton_hwm_select_bank(base, 7); + + pnp_write_hwm5_index(base, 0x01, 0x95); + pnp_write_hwm5_index(base, 0x02, 0x02); + pnp_write_hwm5_index(base, 0x03, 0x30); + + pnp_write_hwm5_index(base, 0x09, 0x5c); +} diff --git a/src/superio/nuvoton/nct6779d/nct6779d_hwm.h b/src/superio/nuvoton/nct6779d/nct6779d_hwm.h new file mode 100644 index 0000000..124f300 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/nct6779d_hwm.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6779D_HWM_H +#define SUPERIO_NUVOTON_NCT6779D_HWM_H + +#include <device/device.h> +#include <device/pnp.h> +#include <device/pnp_type.h> +#include <device/pnp_ops.h> +#include <stdint.h> +#include <superio/conf_mode.h> +#include <superio/hwm5_conf.h> +#include <superio/nuvoton/common/hwm.h> +#include <superio/nuvoton/common/nuvoton.h> + +/* The values correspond to the HWM Bank number for each fan */ +enum nct6779d_hwm_fan { + SYS_FAN = 1, + CPU_FAN = 2, + AUX_FAN0 = 3, + AUX_FAN1 = 8, + AUX_FAN2 = 9, +}; + +/* The values can be directly applied to the HWM registers for fan mode control */ +enum nct6779d_hwm_fan_mode { + FAN_MODE_MANUAL = 0x0 << 4, + FAN_MODE_THERMAL_CRUISE = 0x1 << 4, + FAN_MODE_SPEED_CRUISE = 0x2 << 4, + FAN_MODE_SMART_FAN_IV = 0x4 << 4, +}; + +enum nct6779d_hwm_temp_src { + SYSTIN = 1, + CPUTIN = 2, + AUXTIN0 = 3, + AUXTIN1 = 4, + AUXTIN2 = 5, + AUXTIN3 = 6, + /* Note that value 7 is reserved */ + SMBUSMASTER_0 = 8, + SMBUSMASTER_1 = 9, + SMBUSMASTER_2 = 10, + SMBUSMASTER_3 = 11, + SMBUSMASTER_4 = 12, + SMBUSMASTER_5 = 13, + SMBUSMASTER_6 = 14, + SMBUSMASTER_7 = 15, + PECI_0 = 16, + PECI_1 = 17, + PCH_CHIP_CPU_MAX_TEMP = 18, + PCH_CHIP_TEMP = 19, + PCH_CPU_TEMP = 20, + PCH_MCH_TEMP = 21, + PCH_DIM0_TEMP = 22, + PCH_DIM1_TEMP = 23, + PCH_DIM2_TEMP = 24, + PCH_DIM3_TEMP = 25, + BYTE_TEMP = 26, +}; + +struct nct6779d_hwm_thermal_cruise_params { + u8 target_temp; + u8 tolerance; + u8 start_up_val; + u8 stop_val; + bool stopduty_en; + u8 stop_time; + u8 step_up_time; + u8 step_down_time; + u8 critical_temp; + enum nct6779d_hwm_temp_src temp_src; +}; + +struct nct6779d_hwm_speed_cruise_params { + u16 target_speed; + u8 tolerance; + u8 step_up_time; + u8 step_down_time; +}; + +#if ENV_PNP_SIMPLE_DEVICE +void nct6779d_hwm_init(pnp_devfn_t dev, const u16 base); +#endif + +/* Low level fan control functions */ +static inline void nct6779d_hwm_set_temperature_source( + const u16 base, + const enum nct6779d_hwm_fan fan, + const enum nct6779d_hwm_temp_src temp_src) +{ + nuvoton_hwm_select_bank(base, fan); + pnp_unset_and_set_hwm5_index(base, 0x00, 0x0f, temp_src); +} + +static inline void nct6779d_hwm_set_fan_mode( + const u16 base, + const enum nct6779d_hwm_fan fan, + const enum nct6779d_hwm_fan_mode fan_mode) +{ + nuvoton_hwm_select_bank(base, fan); + pnp_unset_and_set_hwm5_index(base, 0x02, 0xf0, fan_mode); +} + +static inline void nct6779d_hwm_set_temperature_tolerance( + const u16 base, + const enum nct6779d_hwm_fan fan, + const u8 tolerance) +{ + nuvoton_hwm_select_bank(base, fan); + pnp_unset_and_set_hwm5_index(base, 0x02, 0x07, tolerance); +} + +static inline void nct6779d_hwm_set_fan_duty( + const u16 base, + const enum nct6779d_hwm_fan fan, + const u8 speed) +{ + nuvoton_hwm_select_bank(base, fan); + pnp_write_hwm5_index(base, 0x09, speed); +} + +/* Higher order fan control functions */ +void nct6779d_hwm_force_fan_full_on( + const u16 base, + const enum nct6779d_hwm_fan fan); + +void nct6779d_hwm_program_thermal_cruise( + const u16 base, + const enum nct6779d_hwm_fan fan, + const struct nct6779d_hwm_thermal_cruise_params *const tcp); + +void nct6779d_hwm_program_speed_cruise( + const u16 base, + const enum nct6779d_hwm_fan fan, + const struct nct6779d_hwm_speed_cruise_params *const scp); + +void nct6779d_hwm_enable_peci(const u16 base); + +#endif /* SUPERIO_NUVOTON_NCT6779D_HWM_H */
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42435
to look at the new patch set (#2).
Change subject: superio/nuvoton/nct6779d: Add HWM API ......................................................................
superio/nuvoton/nct6779d: Add HWM API
Tested with the usage examples on the Asus P8Z77-V LX2.
Change-Id: I6ddf963638787b6c0041e198576c791618247e9f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p8z77-v_lx2/Kconfig M src/mainboard/asus/p8z77-v_lx2/early_init.c M src/superio/nuvoton/nct6779d/Kconfig M src/superio/nuvoton/nct6779d/Makefile.inc A src/superio/nuvoton/nct6779d/nct6779d_hwm.c A src/superio/nuvoton/nct6779d/nct6779d_hwm.h 6 files changed, 297 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42435/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42435 )
Change subject: superio/nuvoton/nct6779d: Add HWM API ......................................................................
Patch Set 5:
This change is ready for review.
-
Angel Pons (Code Review)