Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46468 )
Change subject: soc/intel/common/acpi: rename uuid for s0ix ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/46468/1/src/soc/intel/common/acpi/l... File src/soc/intel/common/acpi/lpit.asl:
https://review.coreboot.org/c/coreboot/+/46468/1/src/soc/intel/common/acpi/l... PS1, Line 23: c4eb40a0-6cd2-11e2-bcfd-0800200c9a66
This is the "new" UUID for µPEP.
it is the uid for the _DSM function for *any* PEP, see https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_I...
https://review.coreboot.org/c/coreboot/+/46468/1/src/soc/intel/common/acpi/l... PS1, Line 32: 0x60
This indicates only functions 5 and 6 are supported
which is correct
https://review.coreboot.org/c/coreboot/+/46468/1/src/soc/intel/common/acpi/l... PS1, Line 38: Return(Package(5) {0, Ones, Ones, Ones, Ones})
This is where you report the platform requirements for s0ix entry, and I think this may be why s0ix […]
this is not in the scope of this patch series; however, we may revisit that later
https://review.coreboot.org/c/coreboot/+/46468/1/src/soc/intel/common/acpi/l... PS1, Line 44: Return(Buffer(One) {0x0})
This is required to support ACPI S3.
this is also required in Slp_S0, see document mentioned above
If s0ix is disabled, we should just not include this file at all.
it is explained, why this is included in the commit message
This is where you return a list of "bug-check critical devices" such as all SATA/AHCI ports and NVMe drives that support D3cold.
This is not done here but in the mainboard. However we'd need a callback then
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Michael Niewöhner (Code Review)