[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Bill XIE (Code Review)]

Attention is currently required from: Keith Hui.

Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 1:

(1 comment)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/94b8cd65_79772840?usp... :
PS1, Line 67: gpio5 |= 0x20;
> The overridetree could be why. […]

After commenting out "drq 0xf4 = 0xfc" for GPIO5 in overridetree.cb, no device can be detected under PCIe pcie_rp4 (00:00:1c.3) any more regardless of whether a card is present on PCIEX1_2, and LDN 0x09 becomes
idx 30 ... f4 f5 ...
val ff ... 8f a8 ...
def 00 ... ff 00 ...
when a card is present, and
idx 30 ... f4 f5 ...
val ff ... 8f 88 ...
def 00 ... ff 00 ...
when not.