Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45498 )
Change subject: nb/intel/sandybridge: Simplify SPD validity check ......................................................................
nb/intel/sandybridge: Simplify SPD validity check
Instead of decoding the entire SPD, just check the memory type directly.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I3afa0ca5aae984895e50fe7b3792192fdd2ee6c6 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45498/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6d0e845..9ad8fd4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -167,10 +167,8 @@ /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; - printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot);
- spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); - if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) + if (spd[spd_slot][SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) ch_dimms++; }
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45498 )
Change subject: nb/intel/sandybridge: Simplify SPD validity check ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45498 )
Change subject: nb/intel/sandybridge: Simplify SPD validity check ......................................................................
nb/intel/sandybridge: Simplify SPD validity check
Instead of decoding the entire SPD, just check the memory type directly.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I3afa0ca5aae984895e50fe7b3792192fdd2ee6c6 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45498 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 1 insertion(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6d0e845..9ad8fd4 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -167,10 +167,8 @@ /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; - printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot);
- spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); - if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) + if (spd[spd_slot][SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) ch_dimms++; }