Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56088 )
Change subject: mainboard: Add Star Labs labtop series ......................................................................
mainboard: Add Star Labs labtop series
Add support for: LabTop Mk III (kbl-r) LabTop Mk IV (cml) StarBook Mk V (tgl)
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 --- M Documentation/distributions.md M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/labtop.md M MAINTAINERS A src/mainboard/starlabs/Kconfig A src/mainboard/starlabs/Kconfig.name A src/mainboard/starlabs/labtop/Kconfig A src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/Makefile.inc A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/mainboard.asl A src/mainboard/starlabs/labtop/acpi/sleep.asl A src/mainboard/starlabs/labtop/acpi/superio.asl A src/mainboard/starlabs/labtop/board_info.txt A src/mainboard/starlabs/labtop/bootblock.c A src/mainboard/starlabs/labtop/cmos.default A src/mainboard/starlabs/labtop/cmos.layout A src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/hda_verb.c A src/mainboard/starlabs/labtop/mainboard.c A src/mainboard/starlabs/labtop/mainboard.c.save A src/mainboard/starlabs/labtop/ramstage.c A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/spd/spd.h A src/mainboard/starlabs/labtop/spd/spd_util.c A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h A src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/devtree.c A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/gpio.c A src/mainboard/starlabs/labtop/variants/cml/hda_verb.c A src/mainboard/starlabs/labtop/variants/cml/include/variant/ec.h A src/mainboard/starlabs/labtop/variants/cml/romstage.c A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/devtree.c A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/gpio.c A src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c A src/mainboard/starlabs/labtop/variants/kbl/include/variant/ec.h A src/mainboard/starlabs/labtop/variants/kbl/romstage.c A src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc A src/mainboard/starlabs/labtop/variants/tgl/board.fmd A src/mainboard/starlabs/labtop/variants/tgl/data.vbt A src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb A src/mainboard/starlabs/labtop/variants/tgl/devtree.c A src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/tgl/gpio.c A src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c A src/mainboard/starlabs/labtop/variants/tgl/include/variant/ec.h A src/mainboard/starlabs/labtop/variants/tgl/romstage.c 61 files changed, 3,149 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56088/1
diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 5740527..313581a 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -8,6 +8,21 @@
## Hardware shipping with coreboot
+### Purism + +[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and +security; part of that effort is to minimize the amount of proprietary and/or +binary code. Their laptops ship with a blob-free OS and coreboot firmware +with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. + +### Star Labs + +[Star Labs](https://starlabs.systems/) offer a range of laptops designed and +built specifically for Linux. All are now available with coreboot firmware, +using Tianocore as the payload, and which include an NVRAM option to disable +the Intel Management Engine. + +======= ### ChromeOS Devices
All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes, @@ -29,6 +44,13 @@ third party, [3mdeb](https://3mdeb.com). They provide current and tested firmware binaries on [GitHub](https://pcengines.github.io).
+### Star Labs + +[Star Labs](https://starlabs.systems/) offer a range of laptops designed and +built specifically for Linux. All are now available with coreboot firmware, +using Tianocore as the payload, and which include an NVRAM option to disable +the Intel Management Engine. + ### System76
[System76](https://system76.com/) manufactures Linux laptops, desktops, and diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index a08cc43..0900bf6 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -169,6 +169,10 @@
- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
+## Star Labs Systems + +- [Labtop Mk IV / StarBook Mk V](starlabs/labtop.md) + ## Supermicro
- [X10SLM+-F](supermicro/x10slm-f.md) diff --git a/Documentation/mainboard/starlabs/labtop.md b/Documentation/mainboard/starlabs/labtop.md new file mode 100644 index 0000000..0c3fce5 --- /dev/null +++ b/Documentation/mainboard/starlabs/labtop.md @@ -0,0 +1,174 @@ +# Star Labs LabTop + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel i7-10710U (Comet Lake) + - Intel i3-10110U (Comet Lake) + - Intel i7-8550u (Kaby Lake Refresh) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 620 + - GOP driver is recommended, VBT is provided + - eDP 13-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 16GB on-board for Comet Lake platforms[^1] + - 8GB on-board for Kaby Lake Refresh platform. +- Networking + - AX201 CNVi WiFi / Bluetooth soldered to PCBA (Comet Lake) + - 8265 PCIe WiFi / Bluetooth soldered to PCBA (Kaby Lake Refresh) +- Sound + - Realtek ALC256 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1280x720 CCD camera + - USB 3.1 Gen 2 Type-C (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: + +Comet Lake and Kaby Lake configurations: +- Intel Flash Descriptor file (descriptor.bin) +- Intel Management Engine firmware (me.bin) + +Comet Lake configuration only: +- ITE IT8987E firmware (it8987-x.xx.bin) + +All Star Labs platforms: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +##### LabTop Mk IV (Comet Lake) + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml +make +``` + +##### LabTop Mk III (Kaby Lake) + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | no | ++---------------------+------------+ + +#### **Requirements:** + +* Only available on Star Labtop Mk IV and Star LabTop Mk III +* fwupd version 1.5.6 or later +* The battery must be charged to at least 30% +* The charger must be connected (either USB-C or DC Jack) +* BIOS Lock must be disabled +* Supported Linux distribution (Ubuntu 20.04 +, Linux Mint 20.1 + elementaryOS 6 +, Manjaro 21+) + +**fwupd 1.5.6 or later** +To check the version of **fwupd** you have installed, open a terminal window and enter the below command: + +``` +fwupdmgr --version +``` + +This will show the version number. **1.5.6** or greater will work. + +On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: + +``` +sudo add-apt-repository ppa:starlabs/ppa +sudo apt update +sudo apt install fwupd +``` + +On Manjaro: + +``` +sudo pacman -Sy fwupd-git flashrom-starlabs +``` + +Instructions for other distributions will be added once fwupd 1.5.6 is available. If you are not using one of the distributions listed above, it is possible to install coreboot using a Live USB. + +**Disable BIOS Lock** +BIOS Lock must be disabled when switching from the standard AMI (American Megatrends Inc.) firmware to coreboot. To disable BIOS Lock: + +1. Start with your LabTop turned off. Turn it on whilst holding the **F2** key to access the BIOS settings. +2. When the BIOS settings load, use the arrow keys to navigate to the advanced tab. Here you will see BIOS Lock. +3. Press `Enter` to change this setting from **Enabled** to **Disabled** + + + +4. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm. + +#### **Switching Branch** + +Switching branch refers to changing from AMI firmware to coreboot, or vice versa. + +First, check for new firmware files with the below terminal command: + +``` +fwupdmgr refresh --force +``` + +Then, to change branch, enter the below terminal command: + +``` +fwupdmgr switch-branch +``` + +You can then select which branch you would like to use, by typing in the corresponding number: + +You will be prompted to confirm, press `y` to continue or `n` to cancel. + +Once the switch has been completed, you will be prompted to restart. + + +The next reboot can take up to **5 minutes,** do not interrupt this process or disconnect the charger. Once the reboot is complete, that's it - you'll continue to receive updates for whichever branch you are using. + +You can switch branch at any time. diff --git a/MAINTAINERS b/MAINTAINERS index 74f1854..b2fbaca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -446,6 +446,13 @@
+STAR LABS MAINBOARDS +M: Sean Rhodes sean@starlabs.systems +S: Maintained +F: src/mainboard/starlabs/ + + + SYSTEM76 MAINBOARDS M: Jeremy Soller jeremy@system76.com S: Maintained @@ -517,6 +524,11 @@ S: Maintained F: src/ec/lenovo/
+STARLABS EC +M: Sean Rhodes sean@starlabs.systems +S: Maintained +F: src/ec/starlabs/ + SYSTEM76 EC M: Jeremy Soller jeremy@system76.com S: Maintained diff --git a/src/mainboard/starlabs/Kconfig b/src/mainboard/starlabs/Kconfig new file mode 100644 index 0000000..4df0588 --- /dev/null +++ b/src/mainboard/starlabs/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_STARLABS + +choice + prompt "Mainboard model" + +source "src/mainboard/starlabs/*/Kconfig.name" + +endchoice + +source "src/mainboard/starlabs/*/Kconfig" + +config MAINBOARD_VENDOR + default "Star Labs" + +endif # VENDOR_STARLABS diff --git a/src/mainboard/starlabs/Kconfig.name b/src/mainboard/starlabs/Kconfig.name new file mode 100644 index 0000000..7aab0da --- /dev/null +++ b/src/mainboard/starlabs/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_STARLABS + bool "Star Labs" diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig new file mode 100644 index 0000000..73f66b2 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -0,0 +1,112 @@ +if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_STARBOOK_TGL + +# +# LabTop Mk IV CML Board uses the following devices: +# +# GigaDevice GD25Q64C (8192KB) SPI NOR flash (KBL) +# Winbond 25Q128JVSQ (16384KB) SPI NOR flash (CML) +# Infineon SLB9670VQ SPI TPM2.0 device +# Realtek ALC256 audio CODEC +# ITE IT8987 Embedded Controller +# Analogix ANX7447 crosspoint switch +# +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + select BOARD_ROMSIZE_KB_8192 if BOARD_STARLABS_LABTOP_KBL + select DRIVERS_I2C_HID + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select HAVE_SPD_IN_CBFS + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select HAVE_IFD_BIN + select HAVE_ME_BIN + select EC_STARLABS_IT8987 if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_LABTOP_KBL + select EC_STARLABS_IT5570 if BOARD_STARLABS_STARBOOK_TGL + select EC_STARLABS_IT_BIN if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + select SYSTEM_TYPE_LAPTOP + select SPI_FLASH_WINBOND if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + select SPI_FLASH_GIGADEVICE if BOARD_STARLABS_LABTOP_KBL + select DISABLE_ACPI_HIBERNATE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + +config MAINBOARD_DIR + string + default "starlabs/labtop" + +config VARIANT_DIR + string + default "tgl" if BOARD_STARLABS_STARBOOK_TGL + default "cml" if BOARD_STARLABS_LABTOP_CML + default "kbl" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_PART_NUMBER + string + default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL + default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML + default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_FAMILY + string + default "B5" if BOARD_STARLABS_STARBOOK_TGL + default "L4" if BOARD_STARLABS_LABTOP_CML + default "L3" if BOARD_STARLABS_LABTOP_KBL + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "StarBook" if BOARD_STARLABS_STARBOOK_TGL + default "LabTop" + +config DRIVER_TPM_SPI_CHIP + int + default 2 if BOARD_STARLABS_STARBOOK_TGL + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/board.fmd" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(CONFIG_VARIANT_DIR)/flashregion_0_flashdescriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(CONFIG_VARIANT_DIR)/flashregion_2_intel_me.bin" + +config EC_STARLABS_IT_BIN + bool + default n + default y if BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + +config EC_STARLABS_IT_BIN_PATH + string + depends on EC_STARLABS_IT_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/$(CONFIG_VARIANT_DIR)/flashregion_8_ec.bin" + +config UART_FOR_CONSOLE + int + default 2 + +config TIANOCORE_BOOTSPLASH_FILE + string + depends on TIANOCORE_BOOTSPLASH_IMAGE + default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" + +endif diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name new file mode 100644 index 0000000..8ef8b7b --- /dev/null +++ b/src/mainboard/starlabs/labtop/Kconfig.name @@ -0,0 +1,13 @@ +comment "Star Labs LabTop Mk IV" + +config BOARD_STARLABS_STARBOOK_TGL + bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)" + select SOC_INTEL_TIGERLAKE + +config BOARD_STARLABS_LABTOP_CML + bool "Star Labs LabTop Mk IV (i3-10110u and i7-10710u)" + select SOC_INTEL_COMETLAKE_1 + +config BOARD_STARLABS_LABTOP_KBL + bool "Star Labs LabTop Mk IV (i7-8550u)" + select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/starlabs/labtop/Makefile.inc b/src/mainboard/starlabs/labtop/Makefile.inc new file mode 100644 index 0000000..f89bda7 --- /dev/null +++ b/src/mainboard/starlabs/labtop/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += ./spd +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += bootblock.c + +ramstage-y += hda_verb.c +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/starlabs/labtop/acpi/ec.asl b/src/mainboard/starlabs/labtop/acpi/ec.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/acpi/mainboard.asl b/src/mainboard/starlabs/labtop/acpi/mainboard.asl new file mode 100644 index 0000000..db2b32f --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/mainboard.asl @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB) { + #include "sleep.asl" + + /* Power button device. */ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (PBST, One) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } +} + +/* + * The Intel Comet Lake platform doesn't support SoundWire but there + * is a kernel bug in some 5.10.x releases. + * + * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More + * details can be found at https://bit.ly/3ttdffG but it appears to + * be triggered by missing SoundWire ACPI entries. + * + * Add the minimal set to make it work again. + */ +Scope (_SB.PCI0.HDAS) +{ + Device (SNDW) + { + Name (_ADR, 0x40000000) + + Name (_CID, Package (0x02) + { + "PRP00001", + "PNP0A05" + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0B) + } + } +} + +/* + * ITE IT8987E Embedded Controller + * + * We include this here as we need to support different levels within + * the ACPI DSDT tree structure. + */ +#define EC_GPE_SWI 0x49 /* GPP_E15 */ +#define EC_GPE_SCI 0x50 /* GPP_E16 */ + +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) +#include <ec/starlabs/it5570/acpi/ec.asl> +#else +#include <ec/starlabs/it8987/acpi/ec.asl> +#endif diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl new file mode 100644 index 0000000..d8eb818 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + _SB.PCI0.LPCB.H_EC.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + _SB.PCI0.LPCB.H_EC.WAK (Arg0) +} diff --git a/src/mainboard/starlabs/labtop/acpi/superio.asl b/src/mainboard/starlabs/labtop/acpi/superio.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/starlabs/labtop/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/starlabs/labtop/board_info.txt b/src/mainboard/starlabs/labtop/board_info.txt new file mode 100644 index 0000000..9543745 --- /dev/null +++ b/src/mainboard/starlabs/labtop/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Star Labs +Board name: LabTop Mk IV +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/starlabs/labtop/bootblock.c b/src/mainboard/starlabs/labtop/bootblock.c new file mode 100644 index 0000000..ff29429 --- /dev/null +++ b/src/mainboard/starlabs/labtop/bootblock.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <console/console.h> +#include <bootblock_common.h> + +#include "baseboard/variants.h" +//#include "variant/gpio.h" + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/starlabs/labtop/cmos.default b/src/mainboard/starlabs/labtop/cmos.default new file mode 100644 index 0000000..dfd98a3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.default @@ -0,0 +1,19 @@ +# hardcoded +boot_option=Fallback +# console +debug_level=Debug +# cpu +hyper_threading=Enable +vtd=Enable +tdp=15W +me_state=Disable +# Devices +wireless=Enable +webcam=Enable +microphone=Enable +# EC +kbl_timeout=30 seconds +fn_ctrl_swap=Disable +# southbridge +power_on_after_fail=Disable + diff --git a/src/mainboard/starlabs/labtop/cmos.layout b/src/mainboard/starlabs/labtop/cmos.layout new file mode 100644 index 0000000..463f758 --- /dev/null +++ b/src/mainboard/starlabs/labtop/cmos.layout @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 384 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: cpu +400 1 e 1 hyper_threading +401 1 e 1 vtd +402 2 e 7 tdp +404 1 e 5 me_state + +# coreboot config options: Devices +450 1 e 1 wireless +451 1 e 1 webcam +452 1 e 1 microphone + +# coreboot config options: EC +512 3 e 4 kbl_timeout +520 1 e 1 fn_ctrl_swap + +# coreboot config options: southbridge +536 2 e 6 power_on_after_fail +#408 1 h 1 preserve_smmstore + +# coreboot config options: check sums +984 16 h 0 check_sum + +# embedded controller settings (outwith the checksummed area) +1000 1 h 0 fn_lock_state + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +4 0 30 seconds +4 1 1 minute +4 2 3 minutes +4 3 5 minutes +4 4 Never + +5 0 Enable +5 1 Disable + +6 0 Disable +6 1 Enable +6 2 Keep + +7 0 15W +7 1 20W +7 2 25W + +# ----------------------------------------------------------------- +checksums + +checksum 384 983 984 diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl new file mode 100644 index 0000000..69ea246 --- /dev/null +++ b/src/mainboard/starlabs/labtop/dsdt.asl @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> +#if CONFIG(BOARD_STARLABS_LABTOP_CML) || CONFIG(BOARD_STARLABS_STARBOOK_TGL) + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> +#else + #include <soc/intel/skylake/acpi/globalnvs.asl> +#endif + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + /* #include <soc/intel/common/block/acpi/acpi/ipu.asl> */ +#elif CONFIG(BOARD_STARLABS_LABTOP_CML) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> +#else + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> +#endif + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/starlabs/labtop/hda_verb.c b/src/mainboard/starlabs/labtop/hda_verb.c new file mode 100644 index 0000000..c30d75d --- /dev/null +++ b/src/mainboard/starlabs/labtop/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <types.h> + +#define AZALIA_CODEC_ALC256 0x10ec0256 /* 283902550 */ +#define AZALIA_CODEC_ALC269 0x10ec0269 + +const u32 override_verb[] = { + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), +}; + +static void disable_microphone(u8 *base, u32 viddid) +{ + azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb)); +} + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if ((viddid == AZALIA_CODEC_ALC256) || (viddid == AZALIA_CODEC_ALC269)) { + printk(BIOS_DEBUG, "CMOS: viddid = %d\n", viddid); + if (get_uint_option("microphone", 0) == 0) + disable_microphone(base, viddid); + } +} diff --git a/src/mainboard/starlabs/labtop/mainboard.c b/src/mainboard/starlabs/labtop/mainboard.c new file mode 100644 index 0000000..f5f3526 --- /dev/null +++ b/src/mainboard/starlabs/labtop/mainboard.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> +#include <types.h> +#include <uuid.h> +#include <option.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <types.h> +#include <chip.h> +#include <baseboard/variants.h> + +#include "variant/ec.h" + +const char *smbios_mainboard_bios_version(void) +{ + if (CONFIG(BOARD_STARLABS_STARBOOK_TGL)) + return "0"; + else + return "6"; +} + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = it_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +const char *smbios_system_manufacturer(void) +{ + return "Star Labs"; +} + +const char *smbios_system_sku(void) +{ + if (CONFIG(BOARD_STARLABS_STARBOOK_TGL)) + return "B5"; + else if (CONFIG(BOARD_STARLABS_LABTOP_CML)) + return "L4"; + else if (CONFIG(BOARD_STARLABS_LABTOP_KBL)) + return "L3-U"; + else + return "Unknown"; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +const char *smbios_mainboard_location_in_chassis(void) +{ + return "Default"; +} + +const char *smbios_mainboard_asset_tag(void) +{ + return "Default"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +void __weak variant_devtree_update(struct device *nic_dev) +{ +} + +/* Override dev tree settings based on CMOS settings */ +void devtree_update(void) +{ + struct device *nic_dev = NULL; + config_t *cfg = config_of_soc(); + + /* Perform any variant specific changes and return the nic_dev */ + variant_devtree_update(nic_dev); + + if (nic_dev != NULL) { + if (get_uint_option("wireless", 0) == 0) + nic_dev->enabled = 0; + } + + if (get_uint_option("webcam", 0) == 0) + cfg->usb2_ports[6].enable = 0; +} diff --git a/src/mainboard/starlabs/labtop/mainboard.c.save b/src/mainboard/starlabs/labtop/mainboard.c.save new file mode 100644 index 0000000..62b1156 --- /dev/null +++ b/src/mainboard/starlabs/labtop/mainboard.c.save @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> +#include <types.h> +#include <uuid.h> +#include <option.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <types.h> +#include <chip.h> +#include <baseboard/variants.h> +#include <device/azalia_device.h> + +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) +#include <ec/starlabs/it5570/ec.h> +#else +#include <ec/starlabs/it8987/ec.h> +#endif + +#define CODEC_ALC256 0x10ec0256 +#define CODEC_ALC269 0x10ec0269 + +const char *smbios_mainboard_bios_version(void) +{ + return "6"; +} + +/* Get the Embedded Controller firmware version */ +void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision) +{ + u16 ec_version = it_get_version(); + + *ec_major_revision = ec_version >> 8; + *ec_minor_revision = ec_version & 0xff; +} + +const char *smbios_system_manufacturer(void) +{ + return "Star Labs"; +} + +const char *smbios_system_sku(void) +{ +#if CONFIG(BOARD_STARLABS_LABTOP_CML) + return "L4"; +#else + return "L3-U"; +#endif +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +const char *smbios_mainboard_location_in_chassis(void) +{ + return "Default"; +} + +const char *smbios_mainboard_asset_tag(void) +{ + return "Default"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +const char *smbios_chassis_version(void) +{ + return smbios_mainboard_version(); +} + +const char *smbios_chassis_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +/* Override dev tree settings based on CMOS settings */ +void devtree_update(void) +{ + /* + * usb2_ports[2] = Bluetooth + * usb2_ports[6] = Camera + * usb2_ports[9] = CNVi Bluetooth + */ + config_t *cfg = config_of_soc(); + + if (get_uint_option("camera", 0) == 0) + cfg->usb2_ports[6].enable = 0; + + if (get_uint_option("microphone", 0) == 0) + /* Need to switch verb table */ + return; + +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) + struct device *nic = pcidev_on_root(0x1d, 5); +#elif CONFIG(BOARD_STARLABS_LABTOP_CML) + struct device *nic = pcidev_on_root(0x14, 3); +#elif CONFIG(BOARD_STARLABS_LABTOP_KBL) + struct device *nic = pcidev_on_root(0x1c, 5); +#endif + + if (get_uint_option("wireless", 0) == 0) { + nic->enabled = 0; + } + + struct soc_power_limits_config *soc_conf; + soc_conf = &cfg->power_limits_config; + + /* Update PL2 based on CMOS settings */ + switch (get_uint_option("tdp", 0)) { + case 0: + soc_conf->tdp_pl2_override = 15; + break; + case 1: + soc_conf->tdp_pl2_override = 20; + break; + case 2: + soc_conf->tdp_pl2_override = 25; + break; + default: + return; + } +} + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if ((viddid == CODEC_ALC256) || (viddid == CODEC_ALC269)) { + if (get_uint_option("microphone", 0)) + disable_microphone(base); + } +} + +const u32 verbs[] = { + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), +}; + +void disable_microphone(u8 *base) +{ + azalia_program_verb_table(base, , ARRAY_SIZE(standard_verb)); + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); +} + diff --git a/src/mainboard/starlabs/labtop/ramstage.c b/src/mainboard/starlabs/labtop/ramstage.c new file mode 100644 index 0000000..8c7010b --- /dev/null +++ b/src/mainboard/starlabs/labtop/ramstage.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/ramstage.h> +#include <option.h> + +static void init_mainboard(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + devtree_update(); +} + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/starlabs/labtop/spd/Makefile.inc b/src/mainboard/starlabs/labtop/spd/Makefile.inc new file mode 100644 index 0000000..ca39059 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/Makefile.inc @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Schematics for this platform show Samsung K4A8G165WB-BCRC devices +# which are 8Gb, 2400Mbps 512Mx16 devices. +# +# The hardware platforms used for testing are fitted with a Micron part +# which has the FBGA identifier "D9ZFW". The identification tool at +# https://www.micron.com/support/tools-and-utilities/fbga identifies +# this as the MT40A1G16KD-062E:E. These are 16Gb, 1Gx16 devices. +# +# We have defined both SPD options below. +SPD_SOURCES = empty_ddr4 # 0b0000 +SPD_SOURCES += micron-MT40A1G16KD-062E-E # 0b0001 +SPD_SOURCES += empty_ddr4 # 0b0010 +SPD_SOURCES += empty_ddr4 # 0b0011 +SPD_SOURCES += empty_ddr4 # 0b0100 +SPD_SOURCES += empty_ddr4 # 0b0101 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0110 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0111 + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) \ No newline at end of file diff --git a/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex new file mode 100644 index 0000000..1777847 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex new file mode 100644 index 0000000..36b85a2 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex @@ -0,0 +1,33 @@ +# K4A8G165WB-BCRC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 0B E3 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 42 42 30 2D 43 52 43 20 20 20 20 00 80 CE +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/spd.h b/src/mainboard/starlabs/labtop/spd/spd.h new file mode 100644 index 0000000..d334f88 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_SPD_H_ +#define _MAINBOARD_SPD_H_ + +#include <gpio.h> + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/starlabs/labtop/spd/spd_util.c b/src/mainboard/starlabs/labtop/spd/spd_util.c new file mode 100644 index 0000000..fb6ca54 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/spd_util.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <string.h> + +#include "spd.h" + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h new file mode 100644 index 0000000..47e2688 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/memory.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MEMORY_H +#define MEMORY_H + +u8 get_memory_config_straps(void); +const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg); + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h new file mode 100644 index 0000000..cfcc6ab --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/romstage.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_ROMSTAGE_H +#define VARIANT_ROMSTAGE_H + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..cb1f9f9 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BASEBOARD_VARIANTS_H_ +#define _BASEBOARD_VARIANTS_H_ + +#include <soc/gpio.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +void devtree_update(void); +void variant_devtree_update(struct device *nic_dev); + +#endif /* _BASEBOARD_VARIANTS_H_ */ diff --git a/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc new file mode 100644 index 0000000..2a505c3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/labtop/variants/cml/board.fmd b/src/mainboard/starlabs/labtop/variants/cml/board.fmd new file mode 100644 index 0000000..9018104 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/board.fmd @@ -0,0 +1,14 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 16M { + BIOS@0x400000 0xC00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/data.vbt b/src/mainboard/starlabs/labtop/variants/cml/data.vbt new file mode 100644 index 0000000..4040412 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb new file mode 100644 index 0000000..9a5acb5 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb @@ -0,0 +1,182 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + /* Touchpad */ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 15, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# Graphics (soc/intel/cannonlake/graphics.c) + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "3" # 1s + register "PchPmSlpSusMinAssert" = "3" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "10" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_B" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal Device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Not sure + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # SD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port 3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CNVi Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on # CNVi wifi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 off end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Port 2 + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 19.0 off end # I2C4 + device pci 19.1 off end # I2C5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (SSD x4) + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 (LAN) + device pci 1d.5 off end # PCI Express Port 14 (WLAN) + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00fc0201" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x000c0081" + + chip ec/starlabs/it8987 + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on # Intel HDA + subsystemid 0x10ec 0x119e + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/cml/devtree.c b/src/mainboard/starlabs/labtop/variants/cml/devtree.c new file mode 100644 index 0000000..3f33a2e --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/devtree.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <option.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> + +#include "baseboard/variants.h" + +void variant_devtree_update(struct device *nic_dev) +{ + config_t *cfg = config_of_soc(); + struct soc_power_limits_config *soc_conf = &cfg->power_limits_config; + + /* Update PL2 based on CMOS settings */ + switch (get_uint_option("tdp", 0)) { + case 1: + soc_conf->tdp_pl2_override = 20; + break; + case 2: + soc_conf->tdp_pl2_override = 25; + break; + default: + soc_conf->tdp_pl2_override = 15; + break; + } + + /* Return the correct network device for this platform. */ + nic_dev = pcidev_on_root(0x14, 3); +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/cml/gpio.c b/src/mainboard/starlabs/labtop/variants/cml/gpio.c new file mode 100644 index 0000000..18a8ace --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/gpio.c @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "baseboard/variants.h" + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage.c */ +const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_E22, 1, PLTRST), + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), + PAD_CFG_GPI(GPP_H7, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage.c */ +const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 0, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_A7, 0x40100100, 0x3000), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, UP_20K), + PAD_NC(GPP_A19, UP_20K), + PAD_NC(GPP_A20, UP_20K), + PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A22, UP_20K), + PAD_NC(GPP_A23, UP_20K), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), + _PAD_CFG_STRUCT(GPP_B16, 0x80100100, 0x0000), + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPO(GPP_B22, 0, DEEP), + PAD_CFG_GPO(GPP_B23, 1, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C2, 1, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_C5, 0x40880100, 0x0000), + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + _PAD_CFG_STRUCT(GPP_C8, 0x80100100, 0x3000), + _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + _PAD_CFG_STRUCT(GPP_C11, 0x40100100, 0x0000), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_CFG_GPO(GPP_C15, 1, PLTRST), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_D10, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), + PAD_CFG_GPO(GPP_D12, 0, DEEP), + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + PAD_CFG_GPO(GPP_D16, 0, PWROK), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), + PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), + _PAD_CFG_STRUCT(GPP_E3, 0x82040100, 0x0000), + _PAD_CFG_STRUCT(GPP_E4, 0x80880100, 0x3000), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI(GPP_E7, NONE, PLTRST), + PAD_NC(GPP_E8, NONE), + _PAD_CFG_STRUCT(GPP_E9, 0x44001700, 0x0000), + _PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x3000), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_F0, 0x00000301, 0x0000), + PAD_CFG_GPO(GPP_F1, 0, PWROK), + PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), + _PAD_CFG_STRUCT(GPP_F3, 0x84000300, 0x3000), + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPI(GPP_F10, UP_20K, PLTRST), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, UP_20K), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, DN_20K), + PAD_NC(GPP_H0, UP_20K), + PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + PAD_NC(GPP_H3, UP_20K), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + PAD_NC(GPP_H16, NONE), + PAD_CFG_GPO(GPP_H17, 0, DEEP), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000), + PAD_CFG_GPO(GPP_H21, 0, DEEP), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 0, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + diff --git a/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c b/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c new file mode 100644 index 0000000..c89e1df --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <types.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0xffffffff, // Subsystem ID + 33, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID : 0x10EC119E */ + AZALIA_SUBVENDOR(0, 0x10EC119E), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x40700001), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x042b1010), + + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + + /* ALC256 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + + /* ALC256 default-2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + + /* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + 0x02050045, + 0x02045089, + + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + + /* ALC256 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + + /* ALC256 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; + diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/ec.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/ec.h new file mode 100644 index 0000000..2c3ac18 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_EC_H_ +#define _VARIANT_EC_H_ + +#include <ec/starlabs/it8987/ec.h> + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/cml/romstage.c b/src/mainboard/starlabs/labtop/variants/cml/romstage.c new file mode 100644 index 0000000..f41067f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/romstage.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <gpio.h> +#include <string.h> +#include <types.h> + +#include "baseboard/memory.h" + +u8 get_memory_config_straps(void) +{ + /* + * The hardware supports a number of different memory configurations + * which are selected using four ID bits ID3 (GPP_H7), ID2 (GPP_H6), + * ID1 (GPP_E23) and ID0 (GPP_E22). + * + * The mapping is defined in the schematics as follows ID3 is always + * 0 and can be ignored): + * + * ID2ID1ID0Memory type + * -------------------- + * 1 1 1 Samsung 4G single channel + * 1 1 0 Samsung 8G dual channel + * 1 0 1 Micron 4G single channel + * 1 0 0 Micron 8G dual channel + * 0 1 1 Hynix 4G single channel + * 0 1 0 Hynix 8G dual channel + * 0 0 1 Micron 16G dual channel + * 0 0 0 Hynix 16G dual channel + * + * We return the value of these bits so that the index into the SPD + * table can be .spd[] values can be configured correctly in the + * memory configuration structure. + */ + + gpio_t memid_gpios[] = { + GPP_E22, + GPP_E23, + GPP_H6 + }; + return (u8)gpio_base2_value(memid_gpios, ARRAY_SIZE(memid_gpios)); +} + +const struct cnl_mb_cfg *get_memory_cfg(struct cnl_mb_cfg *mem_cfg) +{ + u8 memid; + + struct cnl_mb_cfg std_memcfg = { + /* + * Mainboard uses 121, 81 and 100 rcomp resistors. See R6E1, R6E2 + * and R6E3 on page 6 of the schematics. + */ + .rcomp_resistor = {121, 81, 100}, + + /* + * Mainboard Rcomp target values. + */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* + * Mainboard is a non-interleaved design - see pages 5 & 6 + * of the schematics. + */ + .dq_pins_interleaved = 0, + + /* + * Mainboard is using DDR_VREF_CA for CH_A and DDR1_VREF_DQ for + * CH_B - see page 5 of the schematics. + */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, + }; + + memcpy(mem_cfg, &std_memcfg, sizeof(std_memcfg)); + + memid = get_memory_config_straps(); + printk(BIOS_DEBUG, "Memory config straps: 0x%.2x\n", memid); + + /* + * If we are using single channel ID = 3, 5 or 7 then we only + * populate .spd[0].If we are dual channel then we also populate + * .spd[2] as well. + */ + mem_cfg->spd[0].read_type = READ_SPD_CBFS; + mem_cfg->spd[0].spd_spec.spd_index = memid; + if (memid != 3 && memid != 5 && memid != 7) { + mem_cfg->spd[2].read_type = READ_SPD_CBFS; + mem_cfg->spd[2].spd_spec.spd_index = memid; + } + + return mem_cfg; +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + struct cnl_mb_cfg board_memcfg; + + const uint8_t vtd = get_uint_option("vtd", 1); + memupd->FspmTestConfig.VtdDisable = !vtd; + + const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); + memupd->FspmConfig.HyperThreading = ht; + + cannonlake_memcfg_init(&memupd->FspmConfig, get_memory_cfg(&board_memcfg)); +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc new file mode 100644 index 0000000..8125617 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd new file mode 100644 index 0000000..08bc519 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd @@ -0,0 +1,13 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 8M { + BIOS@0x200000 0x600000 { + RW_MRC_CACHE@0x0 0x10000 + SMMSTORE@0x10000 0x40000 + CONSOLE@0x50000 0x20000 + FMAP@0x70000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt new file mode 100644 index 0000000..0326c91 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb new file mode 100644 index 0000000..0027a1c --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb @@ -0,0 +1,190 @@ +chip soc/intel/skylake + # Disable DEEP + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + + # Enable "Intel Speed Shift Technology" + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + +# Graphics (soc/intel/skylake/graphics.c) + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 0, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 50, + .backlight_off_delay_ms = 0, + .backlight_pwm_hz = 200, + }" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + +# CPU (soc/intel/skylake/chip.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 15, + }" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + # Power + register "PmConfigSlpS3MinAssert" = "3" # 50ms + register "PmConfigSlpS4MinAssert" = "3" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "10" + +# PM Util (soc/intel/skylake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_C" + register "gpe0_dw2" = "GPP_E" + + # Enable the correct decode ranges on the LPC bus. + register "lpc_ioe" = "LPC_IOE_EC_4E_4F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal Device + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # uSD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A port 3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Actual Bluetooth port + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 on end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataSalpSupport" = "0" + register "SataMode" = "0" + + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "0" + + # Port 2 + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "0" + end + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C4 + device pci 19.2 off end # I2C5 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 on # PCI Express Port 6 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + register "PcieRpLtrEnable[5]" = "1" + chip drivers/wifi/generic + device generic 0 on end + end + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9(SSD x4) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "0" + register "PcieRpClkSrcNumber[8]" = "0" + register "PcieRpLtrEnable[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00000069" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x0000006d" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + chip ec/starlabs/it8987 + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + subsystemid 0x10ec 0x111e + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devtree.c b/src/mainboard/starlabs/labtop/variants/kbl/devtree.c new file mode 100644 index 0000000..df45329 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/devtree.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <option.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> + +#include "baseboard/variants.h" + +void variant_devtree_update(struct device *nic_dev) +{ + config_t *cfg = config_of_soc(); + struct soc_power_limits_config *soc_conf = &cfg->power_limits_config; + + /* Update PL2 based on CMOS settings */ + switch (get_uint_option("tdp", 0)) { + case 1: + soc_conf->tdp_pl2_override = 20; + break; + case 2: + soc_conf->tdp_pl2_override = 25; + break; + default: + soc_conf->tdp_pl2_override = 15; + break; + } + + /* Return the correct network device for this platform. */ + nic_dev = pcidev_on_root(0x1c, 5); +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gpio.c b/src/mainboard/starlabs/labtop/variants/kbl/gpio.c new file mode 100644 index 0000000..f60ba0f --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/gpio.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "baseboard/variants.h" + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage. */ +const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + _PAD_CFG_STRUCT(GPD2, 0x04000300, 0x1000), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + _PAD_CFG_STRUCT(GPD7, 0x04000101, 0x1000), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPI(GPD9, DN_20K, PWROK), + PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1), + PAD_CFG_NF(GPD11, DN_20K, PWROK, NF1), + PAD_NC(GPP_A0, NONE), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_NC(GPP_A10, DN_20K), + PAD_CFG_GPI(GPP_A11, DN_20K, DEEP), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, DN_20K), + PAD_NC(GPP_A14, DN_20K), + PAD_NC(GPP_A15, DN_20K), + PAD_NC(GPP_A16, DN_20K), + PAD_NC(GPP_A17, DN_20K), + PAD_NC(GPP_A18, DN_20K), + PAD_NC(GPP_A19, DN_20K), + PAD_NC(GPP_A20, DN_20K), + PAD_NC(GPP_A21, DN_20K), + PAD_NC(GPP_A22, DN_20K), + PAD_NC(GPP_A23, DN_20K), + PAD_NC(GPP_B0, DN_20K), + PAD_NC(GPP_B1, DN_20K), + PAD_NC(GPP_B2, DN_20K), + PAD_NC(GPP_B3, DN_20K), + PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_B6, DN_20K, DEEP), + PAD_CFG_NF(GPP_B7, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1), + PAD_NC(GPP_B11, DN_20K), + PAD_NC(GPP_B12, DN_20K), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_NC(GPP_B14, DN_20K), + PAD_NC(GPP_B15, DN_20K), + PAD_NC(GPP_B16, DN_20K), + PAD_NC(GPP_B17, DN_20K), + PAD_NC(GPP_B18, DN_20K), + PAD_NC(GPP_B19, DN_20K), + PAD_NC(GPP_B20, DN_20K), + PAD_NC(GPP_B21, DN_20K), + PAD_NC(GPP_B22, DN_20K), + PAD_NC(GPP_B23, DN_20K), + PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1), + PAD_NC(GPP_C2, DN_20K), + PAD_NC(GPP_C3, DN_20K), + PAD_NC(GPP_C4, DN_20K), + PAD_NC(GPP_C5, DN_20K), + PAD_NC(GPP_C6, DN_20K), + PAD_NC(GPP_C7, DN_20K), + PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C9, UP_20K, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_C10, 0x44000301, 0x3000), + PAD_CFG_NF(GPP_C11, UP_20K, DEEP, NF1), + PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C13, UP_20K), + PAD_NC(GPP_C14, UP_20K), + PAD_NC(GPP_C15, UP_20K), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_NC(GPP_C22, NONE), + _PAD_CFG_STRUCT(GPP_C23, 0x80100100, 0x3000), + PAD_NC(GPP_D0, DN_20K), + PAD_NC(GPP_D1, DN_20K), + PAD_NC(GPP_D2, DN_20K), + PAD_NC(GPP_D3, DN_20K), + PAD_NC(GPP_D4, DN_20K), + PAD_NC(GPP_D5, DN_20K), + PAD_NC(GPP_D6, DN_20K), + PAD_NC(GPP_D7, DN_20K), + PAD_NC(GPP_D8, DN_20K), + PAD_NC(GPP_D9, DN_20K), + PAD_NC(GPP_D10, DN_20K), + PAD_NC(GPP_D11, DN_20K), + PAD_NC(GPP_D12, DN_20K), + PAD_NC(GPP_D13, DN_20K), + PAD_NC(GPP_D14, DN_20K), + PAD_NC(GPP_D15, DN_20K), + PAD_NC(GPP_D16, DN_20K), + PAD_NC(GPP_D17, DN_20K), + PAD_NC(GPP_D18, DN_20K), + PAD_NC(GPP_D19, DN_20K), + PAD_CFG_TERM_GPO(GPP_D20, 1, UP_20K, DEEP), + PAD_NC(GPP_D21, DN_20K), + PAD_NC(GPP_D22, DN_20K), + PAD_NC(GPP_D23, DN_20K), + PAD_NC(GPP_E0, DN_20K), + PAD_NC(GPP_E1, DN_20K), + _PAD_CFG_STRUCT(GPP_E2, 0x44000601, 0x0000), + PAD_NC(GPP_E3, DN_20K), + PAD_NC(GPP_E4, DN_20K), + PAD_NC(GPP_E5, DN_20K), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, DN_20K), + PAD_NC(GPP_E8, DN_20K), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_NC(GPP_E12, DN_20K), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0000), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + PAD_NC(GPP_E20, DN_20K), + PAD_NC(GPP_E21, DN_20K), + PAD_NC(GPP_E22, DN_20K), + PAD_NC(GPP_E23, DN_20K), + PAD_NC(GPP_F0, DN_20K), + PAD_NC(GPP_F1, DN_20K), + PAD_NC(GPP_F2, DN_20K), + PAD_NC(GPP_F3, DN_20K), + PAD_NC(GPP_F4, DN_20K), + PAD_NC(GPP_F5, DN_20K), + PAD_NC(GPP_F6, DN_20K), + PAD_NC(GPP_F7, DN_20K), + PAD_CFG_NF(GPP_F8, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F9, DN_20K, DEEP, NF1), + PAD_NC(GPP_F10, DN_20K), + PAD_NC(GPP_F11, DN_20K), + PAD_NC(GPP_F12, DN_20K), + PAD_NC(GPP_F13, DN_20K), + PAD_NC(GPP_F14, DN_20K), + PAD_NC(GPP_F15, DN_20K), + PAD_NC(GPP_F16, DN_20K), + PAD_NC(GPP_F17, DN_20K), + PAD_NC(GPP_F18, DN_20K), + PAD_NC(GPP_F19, DN_20K), + PAD_NC(GPP_F20, DN_20K), + PAD_NC(GPP_F21, DN_20K), + PAD_NC(GPP_F22, DN_20K), + PAD_NC(GPP_F23, DN_20K), + PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G4, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G5, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G6, DN_20K, DEEP), + PAD_CFG_GPI(GPP_G7, DN_20K, DEEP), + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c b/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c new file mode 100644 index 0000000..720de44 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <device/azalia.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269 + 0xffffffff, // Subsystem ID + 16, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table */ + AZALIA_SUBVENDOR(0, 0x10EC111E), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x15, 0x042B1010), + AZALIA_PIN_CFG(0, 0x17, 0x411111F0), + AZALIA_PIN_CFG(0, 0x18, 0x04AB1020), + AZALIA_PIN_CFG(0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050018, + 0x02040184, /* Stock: 0x02043984 */ + 0x0205001C, + 0x02040800, + + /* Widget node 0x20 - 1 */ + 0x02050024, + 0x02040000, + 0x02050004, + 0x02040080, + + /* Widget node 0x20 - 2 */ + 0x02050008, + 0x02040300, + 0x0205000C, + 0x02043F00, + + /* Widget node 0x20 - 3 */ + 0x02050015, + 0x02048002, + 0x02050015, + 0x02048002, + + /* Widget node 0x0C */ + 0x00C37080, + 0x00270610, + 0x00D37080, + 0x00370610, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), + +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/labtop/variants/kbl/include/variant/ec.h b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/ec.h new file mode 100644 index 0000000..2c3ac18 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_EC_H_ +#define _VARIANT_EC_H_ + +#include <ec/starlabs/it8987/ec.h> + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c new file mode 100644 index 0000000..2660869 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include "spd/spd_util.c" +#include "spd/spd.h" +#include <ec/acpi/ec.h> +#include <stdint.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + /* Use the correct entry in the SPD table defined in Makefile.inc */ + u8 spd_index = 6; + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + /* struct region_device spd_rdev; */ + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); + if (!mem_cfg->MemorySpdPtr00) + die("spd.bin not found\n"); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc new file mode 100644 index 0000000..2a505c3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/labtop/variants/tgl/board.fmd b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd new file mode 100644 index 0000000..218811b --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd @@ -0,0 +1,18 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 + } + SI_BIOS@0x500000 0xB00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x800 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/data.vbt b/src/mainboard/starlabs/labtop/variants/tgl/data.vbt new file mode 100644 index 0000000..23010a3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb new file mode 100644 index 0000000..09caa7d --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -0,0 +1,217 @@ +chip soc/intel/tigerlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + +# CPU (soc/intel/tigerlake/cpu.c) + # Power limit + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 15, + .tdp_pl4 = 15, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 15, + .tdp_pl4 = 15, + }" + + # Enable heci1 communication + register "HeciEnabled" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # FSP configuration + register "SaGv" = "SaGv_Enabled" + + # CNVi BT enable/disable + register "CnviBtCore" = "true" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Serial I/O + # TODO: Remove ports that are off? + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "3" # 1s + register "PchPmSlpSusMinAssert" = "3" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "10" + + # Enable eDP device + register "DdiPortAConfig" = "1" + + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + + # Disable S0ix + register "s0ix_enable" = "0" + +# PM Util (soc/intel/tigerlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "pmc_gpe0_dw0" = "PMC_GPP_B" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal Device + register "Device4Enable" = "1" + end + device pci 08.0 on end # Gaussian Mixture Model + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # SD Card + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port 3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CNVi Bluetooth + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on # CNVi wifi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C0 + chip drivers/i2c/hid + register "generic.hid" = ""StarPoint"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 on end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "0" + + # Port 2 + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "0" + end + device pci 19.0 off end # I2C4 + device pci 19.1 off end # I2C5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC - not fitted + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9(SSD x4) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 (LAN) + device pci 1d.5 off end # PCI Express Port 14 (WLAN) + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x680 - 0x68F + register "gen1_dec" = "0x000c0681" + # Address 0x88: Decode + register "gen2_dec" = "0x000c1641" + # Address 0x8C: Decode 0x200 - 0x2FF + register "gen3_dec" = "0x00fc0201" + # Address 0x90: Decode 0x80 - 0x8F (Port 80) + register "gen4_dec" = "0x000c0081" + + chip ec/starlabs/it5570 + # Port 4Eh/4Fh + device pnp 4e.0 on # IO Interface + end + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on # Intel HDA + subsystemid 0x10ec 0x119e + register "PchHdaAudioLinkHdaEnable" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c new file mode 100644 index 0000000..445e43e --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <option.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_def.h> + +#include "baseboard/variants.h" + +void variant_devtree_update(struct device *nic_dev) +{ + // TODO: TGL needs power_limits_config[POWER_LIMITS_U_2_CORE] and power_limits_config[POWER_LIMITS_U_4_CORE] + + /* Return the correct network device for this platform. */ + nic_dev = pcidev_on_root(0x1d, 5); +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c new file mode 100644 index 0000000..115ba21 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "baseboard/variants.h" + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in romstage.c */ +const struct pad_config early_gpio_table[] = { + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage.c */ +const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 0, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD11, 0, PWROK), + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), + PAD_NC(GPP_A10, NONE), + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + PAD_NC(GPP_A13, NONE), + PAD_CFG_GPO(GPP_A14, 0, PLTRST), + PAD_NC(GPP_A15, NONE), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_CFG_GPO(GPP_B17, 0, PWROK), + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C2, 0, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C5, 0, DEEP), + PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), + _PAD_CFG_STRUCT(GPP_C8, 0x82800100, 0x0000), + PAD_NC(GPP_C9, NONE), + PAD_CFG_GPO(GPP_C10, 0, PWROK), + PAD_CFG_GPO(GPP_C11, 0, PWROK), + _PAD_CFG_STRUCT(GPP_C12, 0x40800300, 0x1000), + PAD_CFG_GPO(GPP_C13, 1, PLTRST), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NATIVE), + PAD_NC(GPP_D10, NATIVE), + PAD_NC(GPP_D11, NATIVE), + PAD_NC(GPP_D12, NATIVE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + PAD_CFG_GPI(GPP_D17, NONE, DEEP), + PAD_CFG_GPI(GPP_D18, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP), + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI(GPP_E3, NONE, PLTRST), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPO(GPP_E6, 1, PLTRST), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), + _PAD_CFG_STRUCT(GPP_E17, 0x82900100, 0x0000), + PAD_NC(GPP_E18, NATIVE), + PAD_NC(GPP_E19, NATIVE), + PAD_NC(GPP_E20, NATIVE), + PAD_NC(GPP_E21, NATIVE), + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF2), + PAD_CFG_GPO(GPP_E23, 0, DEEP), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_NC(GPP_F8, NONE), + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + PAD_CFG_GPO(GPP_F10, 0, DEEP), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + _PAD_CFG_STRUCT(GPP_F18, 0x82900100, 0x0000), + PAD_NC(GPP_F19, NONE), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + PAD_CFG_GPO(GPP_H0, 0, DEEP), + PAD_CFG_GPO(GPP_H1, 0, DEEP), + PAD_CFG_GPO(GPP_H2, 0, DEEP), + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_GPO(GPP_H23, 0, DEEP), + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_R5, 0, PLTRST), + PAD_CFG_GPO(GPP_R6, 1, PLTRST), + PAD_NC(GPP_R7, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), + PAD_NC(GPP_U4, NONE), + PAD_NC(GPP_U5, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c new file mode 100644 index 0000000..16c6f4c --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <types.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0xffffffff, // Subsystem ID + 0x0000002b, // Number of jacks (NID entries) + + /* Rest Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID Verb-table + HDA Codec Subsystem ID : 0x10EC119E */ + AZALIA_SUBVENDOR(0, 0x10EC119E), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x40700001), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x042b1010), + + /* RESET to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + + /* RESET Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + + /* ALC256 default-1(Class D RESET) */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + + /* ALC256 default-2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + + /* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + 0x02050045, + 0x02045089, + + /* H/W AGC setting-1 */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC2, + + /* H/W AGC setting-2 */ + 0x02050013, + 0x0204401D, + 0x02050016, + 0x02044E50, + + /* Zero data + EAPD to verb-control */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + + /* Zero data */ + 0x02050030, + 0x02048000, + 0x02050030, + 0x02048000, + + /* ALC256 default-3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + + /* ALC256 default-4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + + /* JD1 */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + + /* Microphone + Array MIC security Disable +ADC clock Enable */ + 0x0205000D, + 0x0204A020, + 0x02050005, + 0x02040700, + + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + 0x0205000C, + 0x020401EF, + + /* EQ Bypass + EQ HPF cutoff 250Hz */ + 0x05350000, + 0x0534201A, + 0x0535001d, + 0x05340800, + + /* EQ-2 */ + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341EF8, + + /* EQ-3 */ + 0x05350004, + 0x05340000, + 0x05450000, + 0x05442000, + + /* EQ-4 */ + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + + /* EQ-5 */ + 0x05450003, + 0x05441EF8, + 0x05450004, + 0x05440000, + + /* EQ Update */ + 0x05350000, + 0x0534E01A, + 0x05350000, + 0x0534E01A, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/labtop/variants/tgl/include/variant/ec.h b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/ec.h new file mode 100644 index 0000000..31cd4da --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VARIANT_EC_H_ +#define _VARIANT_EC_H_ + +#include <ec/starlabs/it5570/ec.h> + +#endif diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c new file mode 100644 index 0000000..271d5c5 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <soc/meminit.h> +#include <baseboard/variants.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + /* .rcomp = { + .resistor = 100, + .targets = {40, 30, 33, 33, 30}, + }, */ + + .ect = false, /* Early Command Training */ + + .ddr4_config = { + .dq_pins_interleaved = false, + } +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg *mem_config = &ddr4_mem_config; + const bool half_populated = false; + + const struct mem_spd ddr4_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, + }, + [1] = { + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, + }, + }, + }; + + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); +};
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Sean Rhodes (Code Review)