[M] Change in coreboot[master]: soc/intel/cmn: Store CSE and ISHC version into cbmem table

[Dinesh Gehlot (Code Review)]

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74208 )

Change subject: soc/intel/cmn: Store CSE and ISHC version into cbmem table
......................................................................

soc/intel/cmn: Store CSE and ISHC version into cbmem table

The patch stores the ISHC and CSE version in the CBMEM table. It
verifies CSE has been updated by comparing old and current CSE versions.
If it has, the patch updates the current CSE version in the CBMEM table.
It then updates the CBMEM table with the current ISHC version.

BUG=b:273661726
Test=The current and old cse and ishc versions are verified on the nissa
during cold and warm reboots. Additionally, version updates are verified
by a debug patch that purposely updated the stored cse version.

Signed-off-by: Dinesh Gehlot 
Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 66 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/1

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
index fa5c8d9..4162d84 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
@@ -85,6 +85,7 @@
 #define CBMEM_ID_MEM_CHIP_INFO	0x5048434D
 #define CBMEM_ID_AMD_STB	0x5f425453
 #define CBMEM_ID_AMD_MP2	0x5f32504d
+#define CBMEM_ID_CSE_PARTITION_VERSION 0x43535056

#define CBMEM_ID_TO_NAME_TABLE				 \
    { CBMEM_ID_ACPI,		"ACPI       " }, \
@@ -163,5 +164,6 @@
    { CBMEM_ID_TYPE_C_INFO,		"TYPE_C INFO"},\
    { CBMEM_ID_MEM_CHIP_INFO,       "MEM CHIP INFO"},\
    { CBMEM_ID_AMD_STB,		"AMD STB"},\
-	{ CBMEM_ID_AMD_MP2,		"AMD MP2 BUFFER"}
+	{ CBMEM_ID_AMD_MP2,		"AMD MP2 BUFFER"},\
+	{ CBMEM_ID_CSE_PARTITION_VERSION, "CSE PARTITION VERSION"}
 #endif /* _CBMEM_ID_H_ */
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 4a624e6..3ebb871 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -186,7 +186,6 @@
    return CB_SUCCESS;
 }

-
 static uint8_t cse_get_current_bp(const struct cse_bp_info *cse_bp_info)
 {
    return cse_bp_info->current_bp;
@@ -198,6 +197,34 @@
    return &cse_bp_info->bp_entries[bp];
 }

+static void store_ishc_version(void)
+{
+	struct cse_fw_partition_info *version;
+	version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION);
+	size_t vers_size = sizeof(struct fw_version);
+
+	/*compare if stored cse version is same as current cse*/
+	if (memcmp(&version->ish_info.pre_cse, &version->curr_cse, vers_size)) {
+		struct fw_version_resp resp;
+		if (cse_get_partition_info(FPT_PARTITION_NAME_ISHC, &resp)) {
+			/*update stored cse version with current version*/
+			memcpy(&version->ish_info.pre_cse, &version->curr_cse, vers_size);
+			/*since cse version has been updated, ishc version needs to be updated.*/
+			memcpy(&version->ish_info.curr_ish, &(resp.manifest_data.version), vers_size);
+		}
+	}
+}
+
+static void store_cse_version(const struct fw_version *live_cse)
+{
+	struct cse_fw_partition_info *version = NULL;
+	uint32_t id = CBMEM_ID_CSE_PARTITION_VERSION;
+
+	version = cbmem_add(id, sizeof(struct cse_fw_partition_info));
+	/*update current cse version*/
+	memcpy(&version->curr_cse, live_cse, sizeof(struct fw_version));
+}
+
 static void cse_print_boot_partition_info(const struct cse_bp_info *cse_bp_info)
 {
    const struct cse_bp_entry *cse_bp;
@@ -223,6 +250,8 @@
    		cse_bp->fw_ver.hotfix, cse_bp->fw_ver.build,
    		cse_bp->status, cse_bp->start_offset,
    		cse_bp->end_offset);
+
+	store_cse_version(&(cse_bp->fw_ver));
 }

/*
@@ -1150,6 +1179,7 @@
    	printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n");
    	cse_trigger_vboot_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR);
    }
+	store_ishc_version();
 }

static void ramstage_cse_fw_sync(void *unused)
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 3f3bab3..57573c7 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -142,6 +142,18 @@
    struct flash_partition_data manifest_data;
 };

+/* ISHC version */
+struct cse_fw_ish_version_info {
+	struct fw_version pre_cse;
+	struct fw_version curr_ish;
+};
+
+/* CSE and ISHC version */
+struct cse_fw_partition_info {
+	struct fw_version curr_cse;
+	struct cse_fw_ish_version_info ish_info;
+};
+
 /* CSE RX and TX error status */
 enum cse_tx_rx_status {
    /*