Change in coreboot[master]: [WIP]soc/intel/tigerlake: Update C-state latencies

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coreboot-gerrit@coreboot.org

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participants (6)
  • Duncan Laurie (Code Review)
  • Furquan Shaikh (Code Review)
  • Paul Menzel (Code Review)
  • Ravishankar Sarawadi (Code Review)
  • Shreesh Chhabbi (Code Review)
  • Wonkyu Kim (Code Review)