Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: [WIP]soc/intel/tigerlake: Update C-state latencies ......................................................................
[WIP]soc/intel/tigerlake: Update C-state latencies
Update newly recommended C-state latency values.
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e --- M src/soc/intel/tigerlake/include/soc/cpu.h 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43316/1
diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 28dfb38..47a41eb 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -7,11 +7,11 @@
/* Latency times in us */ #define C1_LATENCY 1 -#define C6_LATENCY 127 -#define C7_LATENCY 253 -#define C8_LATENCY 260 -#define C9_LATENCY 487 -#define C10_LATENCY 1048 +#define C6_LATENCY 121 +#define C7_LATENCY 152 +#define C8_LATENCY 256 +#define C9_LATENCY 340 +#define C10_LATENCY 1034
/* Power in units of mW */ #define C1_POWER 0x3e8
Hello build bot (Jenkins), Shreesh Chhabbi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43316
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per BWG doc#611569 section-4.6.3.2.2 .
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e --- M src/soc/intel/tigerlake/include/soc/cpu.h 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43316/2
Hello build bot (Jenkins), Shreesh Chhabbi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43316
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per BWG doc#611569 section-4.6.3.2.2 .
BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e --- M src/soc/intel/tigerlake/include/soc/cpu.h 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43316/4
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
Patch Set 4: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43316/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43316/4//COMMIT_MSG@10 PS4, Line 10: BWG doc#611569 section-4.6.3.2.2 . Nice. One nit: Please remove the minus after section.
Hello build bot (Jenkins), Wonkyu Kim, Shreesh Chhabbi, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43316
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per BWG doc#611569 section 4.6.3.2.2 .
BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e --- M src/soc/intel/tigerlake/include/soc/cpu.h 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43316/5
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
Patch Set 5:
Please help to review. These are updated latency values which are improving deeper C-State residencies in idle.
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
Patch Set 5: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43316/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43316/5//COMMIT_MSG@10 PS5, Line 10: 4.6.3.2.2 from Rev 0.8 section# is changed to 4.5.3.2.2
Shreesh Chhabbi has uploaded a new patch set (#6) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per BWG Rev 0.8: section 4.5.3.2.2 & doc#611569: section 4.6.3.2.2
BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e --- M src/soc/intel/tigerlake/include/soc/cpu.h 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43316/6
Wonkyu Kim has uploaded a new patch set (#7) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per BWG(611569) Rev 0.8: section 4.5.3.2.2
BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e --- M src/soc/intel/tigerlake/include/soc/cpu.h 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43316/7
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
Patch Set 7: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/43316/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43316/4//COMMIT_MSG@10 PS4, Line 10: BWG doc#611569 section-4.6.3.2.2 .
Nice. One nit: Please remove the minus after section.
Done
https://review.coreboot.org/c/coreboot/+/43316/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43316/5//COMMIT_MSG@10 PS5, Line 10: 4.6.3.2.2
from Rev 0.8 section# is changed to 4.5.3.2. […]
Done
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
Patch Set 7:
Could this be merged if no more reviews pending?
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43316 )
Change subject: soc/intel/tigerlake: Update Pkg C-State latencies ......................................................................
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per BWG(611569) Rev 0.8: section 4.5.3.2.2
BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43316 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Shreesh Chhabbi shreesh.chhabbi@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/include/soc/cpu.h 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Wonkyu Kim: Looks good to me, approved Shreesh Chhabbi: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 28dfb38..47a41eb 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -7,11 +7,11 @@
/* Latency times in us */ #define C1_LATENCY 1 -#define C6_LATENCY 127 -#define C7_LATENCY 253 -#define C8_LATENCY 260 -#define C9_LATENCY 487 -#define C10_LATENCY 1048 +#define C6_LATENCY 121 +#define C7_LATENCY 152 +#define C8_LATENCY 256 +#define C9_LATENCY 340 +#define C10_LATENCY 1034
/* Power in units of mW */ #define C1_POWER 0x3e8