New subject: Change in coreboot[master]: WIP: skylake-sp: Add uncore and memory map

19 Feb 2020

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38985 )
Change subject: WIP: Add VTD
......................................................................
WIP: Add VTD
Change-Id: If3cb271a974f06d24ff17987595b700e7bdadc47
---
M src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc
M src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c
M src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h
A src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h
A src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h
A src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c
6 files changed, 425 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38985/1

diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc
index 50da224..053f372 100644
--- a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc
+++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc
@@ -13,7 +13,7 @@
 ##
romstage-y += romstage.c
-ramstage-y += chip.c
+ramstage-y += chip.c mmapvtd.c
CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include
 CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include
diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c
index 52488d8..10a6855 100644
--- a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c
+++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c
@@ -18,6 +18,9 @@
 #include <device/device.h>
 #include <fsp/api.h>
 #include <lib.h>
+#include <device/pci_ops.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
static void skxsp_pci_domain_read_resources(struct device *dev)
 {
diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h
index fba62a3..b97f4f8 100644
--- a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h
+++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h
@@ -32,4 +32,22 @@
 #define PCH_DEV_LPC	_PCH_DEV(LPC, 0)
 #define PCH_DEV_P2SB	_PCH_DEV(LPC, 1)
+/* Skylake SP devices, registers */
+#define SKXSP_MMAP_VTD_CFG_REG_DEVID 		0x2024
+#define SKXSP_VTD_DEV				5
+#define SKXSP_VTD_FUNC				0
+#define SKXSP_VTD_MMCFG_BASE_CSR		0x90
+#define SKXSP_VTD_MMCFG_LIMIT_CSR		0x98
+#define SKXSP_VTD_TSEG_BASE_CSR			0xa8
+#define SKXSP_VTD_TSEG_LIMIT_CSR		0xac
+#define SKXSP_VTD_TOLM_CSR			0xd0
+#define SKXSP_VTD_TOHM_CSR			0xd4
+#define SKXSP_VTD_MMIOL_CSR			0xdc
+#define SKXSP_VTD_ME_BASE_CSR			0xf0
+#define SKXSP_VTD_ME_LIMIT_CSR			0xf8
+#define SKXSP_SAD_ALL_DEV			29
+#define SKXSP_SAD_ALL_FUNC			0
+#define SKXSP_SAD_ALL_PAM0123_CSR		0x40
+#define SKXSP_SAD_ALL_PAM456_CSR		0x44
+
 #endif
diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h
new file mode 100644
index 0000000..7b994ca
--- /dev/null
+++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Facebook Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _SKYLAKESP_IOMAP_H_
+#define _SKYLAKESP_IOMAP_H_
+
+#define APEI_ERST_BASE_ADDRESS		0x6a7a9000
+#define APEI_ERST_BASE_SIZE		(0x6c8a8fff - APEI_ERST_BASE_ADDRESS + 1)
+
+#endif
diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h
new file mode 100644
index 0000000..4b72e231
--- /dev/null
+++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SKX_LOG_UTILS_H_
+#define _SKX_LOG_UTILS_H_
+
+#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \
+	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
+	__func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), (base_kb << 10) + (size_kb << 10) - 1, size_kb)
+
+#define LOG_IO_RESOURCE(type, dev, index, base, size) \
+	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
+	__func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size)
+
+#define ADD_MMIO_RESOURCE(dev, index, base, size) \
+	mmio_resource(dev, index, (uint64_t) ((uint64_t)base >> 10), (uint64_t) ((uint64_t)size >> 10)); \
+	LOG_MEM_RESOURCE("mmio", dev, index,  (uint64_t) ((uint64_t)base >> 10), (uint64_t) ((uint64_t)size >> 10))
+
+#endif
diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c
new file mode 100644
index 0000000..cebf488
--- /dev/null
+++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c
@@ -0,0 +1,349 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Facebook Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/lapic.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <fsp/memory_init.h>
+#include <fsp/util.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/skx_iomap.h>
+#include <soc/skx_log_utils.h>
+
+#define MAP_ENTRY(reg_, is_64_, is_limit_, mask_bits_, desc_)			\
+	{									\
+		.reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_,	\
+		.mask_bits = mask_bits_, .description = desc_,			\
+	}
+
+#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 0, desc_)
+#define MAP_ENTRY_LIMIT_64(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_)
+#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 0, desc_)
+#define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_)
+
+struct map_entry {
+	int reg;
+	int is_64_bit;
+	int is_limit;
+	int mask_bits;
+	const char *description;
+};
+
+enum {
+	TOHM_REG,
+	MMIOL_REG,
+	MMCFG_BASE_REG,
+	MMCFG_LIMIT_REG,
+	TOLM_REG,
+	ME_BASE_REG,
+	ME_LIMIT_REG,
+	TSEG_BASE_REG,
+	TSEG_LIMIT_REG,
+	/* Must be last. */
+	NUM_MAP_ENTRIES
+};
+
+static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
+		[TOHM_REG] = MAP_ENTRY_LIMIT_64(SKXSP_VTD_TOHM_CSR, 26, "TOHM"),
+		[MMIOL_REG] = MAP_ENTRY_BASE_32(SKXSP_VTD_MMIOL_CSR, "MMIOL"),
+		[MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(SKXSP_VTD_MMCFG_BASE_CSR, "MMCFG_BASE"),
+		[MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(SKXSP_VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"),
+		[TOLM_REG] = MAP_ENTRY_LIMIT_32(SKXSP_VTD_TOLM_CSR, 26, "TOLM"),
+		[ME_BASE_REG] = MAP_ENTRY_BASE_64(SKXSP_VTD_ME_BASE_CSR, "ME_BASE"),
+		[ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(SKXSP_VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"),
+		[TSEG_BASE_REG] = MAP_ENTRY_BASE_32(SKXSP_VTD_TSEG_BASE_CSR, "TSEGMB_BASE"),
+		[TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(SKXSP_VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"),
+};
+
+static void read_map_entry(struct device *dev, struct map_entry *entry,
+							uint64_t *result)
+{
+	uint64_t value;
+	uint64_t mask;
+
+	/* All registers are on a 1MiB granularity. */
+	mask = ((1ULL << entry->mask_bits) - 1);
+	mask = ~mask;
+
+	value = 0;
+
+	if (entry->is_64_bit) {
+		value = pci_read_config32(dev, entry->reg + 4);
+		value <<= 32;
+	}
+
+	value |= (uint64_t)pci_read_config32(dev, entry->reg);
+	value &= mask;
+
+	if (entry->is_limit)
+		value |= ~mask;
+
+	*result = value;
+}
+
+static void mc_read_map_entries(struct device *dev, uint64_t *values)
+{
+	int i;
+	for (i = 0; i < NUM_MAP_ENTRIES; i++)
+		read_map_entry(dev, &memory_map[i], &values[i]);
+}
+
+static void mc_report_map_entries(struct device *dev, uint64_t *values)
+{
+	int i;
+	for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+		printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
+			memory_map[i].description, values[i]);
+	}
+}
+
+/*
+ * Host Memory Map:
+ *
+ * +--------------------------+ TOCM (2 pow 46 - 1)
+ * |     Reserved             |
+ * +--------------------------+
+ * |     MMIOH (relocatable)  |
+ * +--------------------------+
+ * |     PCISeg               |
+ * +--------------------------+ TOHM
+ * |    High DRAM Memory      | (0x100000000 - 0x107fffffff, 0x3e00000)
+ * +--------------------------+ 4GiB (0x100000000)
+ * +--------------------------+ 0xFFFF_FFFF
+ * |     Firmware             | (0xff000000 - 0xffffffff, 0x4000)
+ * +--------------------------+ 0xFF00_0000
+ * |     Reserved             |
+ * +--------------------------+ 0xFEF0_0000
+ * |     Local xAPIC          | (0xfee00000 - 0xfee00fff, 0x4) ** wrong?
+ * |     Local xAPIC          | (0xfee00000 - 0xfeefffff, 0x400)
+ * +--------------------------+ 0xFEE0_0000
+ * |     HPET/LT/TPM/Others   | (0xfed00000 - 0xfedfffff, 0x400)
+ * +--------------------------+ 0xFED0_0000
+ * |     I/O xAPIC            | (0xfec00000 - 0xfecfffff, 0x400)
+ * |     I/O xAPIC            | (0xfec01000 - 0xfed00fff, 0x400 - wrong??)
+ * |     I/O xAPIC            | (0xfec00000 - 0xfec00fff, 0x4 - wrong??)
+			IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23
+			IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 24-31
+			IOAPIC[2]: apic_id 10, version 32, address 0xfec08000, GSI 32-39
+			IOAPIC[3]: apic_id 11, version 32, address 0xfec10000, GSI 40-47
+			IOAPIC[4]: apic_id 12, version 32, address 0xfec18000, GSI 48-55
+			IOAPIC[5]: apic_id 15, version 32, address 0xfec20000, GSI 72-79
+			IOAPIC[6]: apic_id 16, version 32, address 0xfec28000, GSI 80-87
+			IOAPIC[7]: apic_id 17, version 32, address 0xfec30000, GSI 88-95
+			IOAPIC[8]: apic_id 18, version 32, address 0xfec38000, GSI 96-103
+ * +--------------------------+ 0xFEC0_0000
+ * |     Reserved             |  (0xfeb80000 - 0xfebfffff, 0x200)
+ * +--------------------------+ 0xFEB8_0000
+ * |     Reserved             | (0xfeb0)0000 - 0xfeb0_ffff, 0x40) ** wrong?
+ * +--------------------------+ 0xFEB0_0000
+ * |     Reserved             | (0xfe000000, 0x10000, PCI: 00:1f.2,) - ??
+			00:1f.5 Intel Corporation Lewisburg SPI Controller
+			Memory at fe010000 (32-bit, non-prefetchable) [size=4K]
+ * +--------------------------+ 0xFE00_0000
+ * |     MMIOL (relocatable)  |
+ * |     P2SB PCR cfg BAR     | (0xfd000000 - 0xfdffffff
+ * |     BAR space            | [mem 0x90000000-0xfcffffff] available for PCI devices
+ * +--------------------------+ 0x9000_0000
+ * |PCIe MMCFG (relocatable)  | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
+ * +--------------------------+ TOLM
+ * |     MEseg (relocatable)  | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000)
+ * +--------------------------+
+ * |     Tseg (relocatable)   | N x 8MB (0x70000000 - 0x77ffffff, 0x20000)
+ * +--------------------------+
+ * |     Reserved - CBMEM     | (0x6fffe000 - 0x6fffffff, 0x2000)
+ * +--------------------------+
+ * |     Reserved - FSP       | (0x6fbfe000 - 0x6fffdfff, 0x400000)
+ * +--------------------------+ top_of_ram (0x6fbfdfff)
+ * |     Low DRAM Memory      | (0x100000 - 0x6fbfdfff, 0x1bebf8)
+ * +--------------------------+ FFFFF (1MB)
+ * |     E & F segments       |
+ * +--------------------------+ E0000
+ * |     C & D segments       |
+ * +--------------------------+ C0000
+ * |     VGA & SMM Memory     |
+ * +--------------------------+ A0000
+ * |    Conventional Memory   |
+ * |      (DOS Range)         | reserved =? nosave memory: [mem 0x00000000-0x00000fff]
+ * +--------------------------+ 0
+ */
+
+static void mc_add_dram_resources(struct device *dev, int *res_count)
+{
+	struct range_entry fsp_mem;
+	uint64_t base_kb;
+	uint64_t size_kb;
+	uint64_t top_of_ram;
+	uint64_t mc_values[NUM_MAP_ENTRIES];
+	struct resource *resource;
+	int index = *res_count;
+
+	fsp_find_reserved_memory(&fsp_mem);
+
+	/* Read in the MAP registers and report their values. */
+	mc_read_map_entries(dev, &mc_values[0]);
+	mc_report_map_entries(dev, &mc_values[0]);
+
+	top_of_ram = range_entry_base(&fsp_mem) - 1;
+	printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
+				 range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
+
+	/* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */
+	base_kb = 0;
+	size_kb = (0xa0000 >> 10);
+	LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb);
+	ram_resource(dev, index++, base_kb, size_kb);
+
+	/* 1MB -> top_of_ram i.e., fsp_mem_base+1*/
+	base_kb = (0x100000 >> 10);
+	size_kb = (top_of_ram - 0xfffff) >> 10;
+	LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb);
+	ram_resource(dev, index++, base_kb, size_kb);
+
+	/*
+	 * Add CBMem, FSP Memory, TSEG/MESEG Regions as reserved memory
+	 * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM resered size
+	 * 	  arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE
+	 *    typically 0x2000
+	 *  Example config:
+	 *  FSP_RESERVED_MEMORY_RESOURCE_HOB
+	 *     FspReservedMemoryResource Base : 6FBFE000
+	 *     FspReservedMemoryResource Size : 400000
+	 *  FSP_BOOT_LOADER_TOLUM_HOB
+	 *     FspBootLoaderTolum Base : 6FFFE000
+	 *     FspBootLoaderTolum Size : 2000
+	 */
+
+	/* Mark FSP region */
+	base_kb = (range_entry_base(&fsp_mem) >> 10);
+	size_kb = (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1) >> 10;
+	LOG_MEM_RESOURCE("mmio_fsp", dev, index, base_kb, size_kb);
+	mmio_resource(dev, index++, base_kb, size_kb);
+
+	/* Mark coreboot region as reserved */
+	base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
+	size_kb = (mc_values[TSEG_BASE_REG] - (base_kb << 10)) >> 10;
+	LOG_MEM_RESOURCE("mmio_coreboot", dev, index, base_kb, size_kb);
+	mmio_resource(dev, index++, base_kb, size_kb);
+
+	/* Mark TSEG/SMM region */
+	base_kb = (mc_values[TSEG_BASE_REG] >> 10);
+	size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10;
+	LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb);
+	mmio_resource(dev, index++, base_kb, size_kb);
+
+	/* Mark region between TSEG - TOLM as reserved */
+	if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) {
+		base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10);
+		size_kb = (mc_values[TOLM_REG] - mc_values[TSEG_LIMIT_REG]) >> 10;
+		LOG_MEM_RESOURCE("mmio_tolm", dev, index, base_kb, size_kb);
+		mmio_resource(dev, index++, base_kb, size_kb);
+	}
+
+	/* 4GiB -> TOHM */
+	if (mc_values[TOHM_REG] > 0x100000000) {
+		base_kb = (0x100000000 >> 10);
+		size_kb = (mc_values[TOHM_REG] - 0x100000000 + 1) >> 10;
+		LOG_MEM_RESOURCE("high_ram", dev, index, base_kb, size_kb);
+		ram_resource(dev, index++, base_kb, size_kb);
+	}
+
+	/* add MMIO CFG resource */
+	resource = new_resource(dev, index++);
+	resource->base = (resource_t) mc_values[MMCFG_BASE_REG];
+	resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+								IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
+
+	/* add Local APIC resource */
+	resource = new_resource(dev, index++);
+	resource->base = LAPIC_DEFAULT_BASE;
+	resource->size = 0x00001000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+							IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
+
+	/* add legacy region as reserved - 0xa000 - 1MB */
+	base_kb = (0xa0000 >> 10);
+	size_kb = (0x100000 - 0xa0000) >> 10;
+	LOG_MEM_RESOURCE("legacy_mmio", dev, index, base_kb, size_kb);
+	mmio_resource(dev, index++, base_kb, size_kb);
+
+	/* add APEI_ERST reserved region */
+	/*
+		 Error Record Serialization Table (ERST) support is initialized
+		 APEI firmware first mode is enabled by APEI bit and WHEA _OSC
+		 6a7a9000-6c8a8fff : Reserved
+		 6b88e018-6b88e018 : APEI ERST
+		 6b88e01c-6b88e021 : APEI ERST
+		 6b88e028-6b88e039 : APEI ERST
+		 6b88e040-6b88e04c : APEI ERST
+	*/
+
+	resource = new_resource(dev, index++);
+	resource->base = APEI_ERST_BASE_ADDRESS;
+	resource->size = APEI_ERST_BASE_SIZE;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+							IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
+
+	*res_count = index;
+}
+
+static void mmapvtd_read_resources(struct device *dev)
+{
+	int index = 0;
+
+	/* Read standard PCI resources. */
+	pci_dev_read_resources(dev);
+
+	/* Calculate and add DRAM resources. */
+	mc_add_dram_resources(dev, &index);
+}
+
+static void mmapvtd_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "mmapvtd_init\n");
+}
+
+struct pci_operations soc_pci_ops = {
+	.set_subsystem = &pci_dev_set_subsystem
+};
+
+static struct device_operations mmapvtd_ops = {
+	.read_resources    = mmapvtd_read_resources,
+	.set_resources     = pci_dev_set_resources,
+	.enable_resources  = pci_dev_enable_resources,
+	.init              = mmapvtd_init,
+	.ops_pci           = &soc_pci_ops,
+};
+
+static const unsigned short mmapvtd_ids[] = {
+	SKXSP_MMAP_VTD_CFG_REG_DEVID, /* Memory Map/Intel® VT-d Configuration Registers */
+	0
+};
+
+static const struct pci_driver mmapvtd_driver __pci_driver = {
+	.ops      = &mmapvtd_ops,
+	.vendor   = PCI_VENDOR_ID_INTEL,
+	.devices  = mmapvtd_ids
+};
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If3cb271a974f06d24ff17987595b700e7bdadc47
Gerrit-Change-Number: 38985
Gerrit-PatchSet: 1
Gerrit-Owner: Andrey Petrov anpetrov@fb.com
Gerrit-Reviewer: Andrey Petrov anpetrov@fb.com
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    

Change in coreboot[master]: WIP: Add VTD