Change in coreboot[4.11_branch]: soc/intel/broadwell_de: Re-read SPD on CRC error

[Andrey Petrov (Code Review)]

Hello Werner Zeh, Patrick Rudolph, David Hendricks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37303

to look at the new patch set (#2).

Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error
......................................................................

soc/intel/broadwell_de: Re-read SPD on CRC error

I2C bus does not guarantee data integrity. As result, sometimes
we end up detecting CRC errors and not adding DIMMs to SMBIOS tables.
This change adds re-tries on such errors.

TEST=let OCP monolake run without fan and try reading SPD data in tight
loop. CRC errors were reported but subsequent retries were error free.

Change-Id: I650c8cd80f75b603db332024748a91af6171f096
Signed-off-by: Andrey Petrov 
---
M src/soc/intel/fsp_broadwell_de/romstage/memory.c
1 file changed, 21 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37303/2