[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware

[Arthur Heymans (Code Review)]

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70265 )

Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware
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Patch Set 3:

(2 comments)

File src/soc/intel/common/block/acpi/acpi.c:

https://review.coreboot.org/c/coreboot/+/70265/comment/c769dce8_0a31a0e6 
PS1, Line 96: 		current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]);
> Currently GSIs are assigned in the order these calls are made. There are some assumptions that GSIs 0-15 are connected to legacy IRQs, so the first IOAPIC on the table needs to be the one delivering superio SERIRQs, i8254(?) timer etc.
>
> Could already be the case, I did not dig into soc_get_ioapic_info() and the HOBs to say.

That is currently true. The first IOAPIC reported is the PCH one which has the 0-15 GSI.

File src/soc/intel/xeon_sp/acpi.c:

https://review.coreboot.org/c/coreboot/+/70265/comment/11043f2a_1df6fda8 
PS1, Line 99: 	xeonsp_ioapic_bases[index++] = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase;
> With XEON_SP_HAVE_IIO_IOAPIC=y, does this get added again at index 1, and emit associated MADT entries twice?
>
> I have no clue what is_iio_stack_res() checks.

iio_stack_res are the resources on a PCI root bridge that Intel call IIO stack.

I forgot:
if (stack == 0 && socket == 0)
    			madt_tbl[cur_index].addr += 0x1000;