Change in coreboot[master]: icelake: remove unused processor power limits configuration

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41236 )

Change subject: icelake: remove unused processor power limits configuration
......................................................................

icelake: remove unused processor power limits configuration

Remove unused processor power limit configuration parameter
and function call based on common code base support for
Intel Icelake SoC based platform.

BRANCH=None
BUG=None
TEST=Built for icelake based dragonegg board.

Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8
Signed-off-by: Sumeet R Pawnikar 
---
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/include/soc/cpu.h
2 files changed, 0 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/41236/1

diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index 67d7ff5..bf8678f 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -172,8 +172,6 @@
    /* HeciEnabled decides the state of Heci1 at end of boot
     * Setting to 0 (default) disables Heci1 and hides the device from OS */
    uint8_t HeciEnabled;
-	/* PL2 Override value in Watts */
-	uint32_t tdp_pl2_override;
    /* Intel Speed Shift Technology */
    uint8_t speed_shift_enable;
    /* Enable VR specific mailbox command
diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h
index 30df00a..33443c4 100644
--- a/src/soc/intel/icelake/include/soc/cpu.h
+++ b/src/soc/intel/icelake/include/soc/cpu.h
@@ -31,7 +31,4 @@
    C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
    			      (IRTL_1024_NS >> 10))

-/* Configure power limits for turbo mode */
-void set_power_limits(u8 power_limit_1_time);
-
 #endif

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41236 )

Change subject: icelake: remove unused processor power limits configuration
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41236/1/src/soc/intel/icelake/chip.... 
File src/soc/intel/icelake/chip.h:

https://review.coreboot.org/c/coreboot/+/41236/1/src/soc/intel/icelake/chip.... 
PS1, Line 175: 	/* Intel Speed Shift Technology */
What about soc_power_limits_config, and then fixing up google/dragonegg, and intel/icelake_rvp ?

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41236 )

Change subject: icelake: remove unused processor power limits configuration
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41236/1/src/soc/intel/icelake/chip.... 
File src/soc/intel/icelake/chip.h:

https://review.coreboot.org/c/coreboot/+/41236/1/src/soc/intel/icelake/chip.... 
PS1, Line 175: 	/* Intel Speed Shift Technology */
> What about soc_power_limits_config, and then fixing up google/dragonegg, and intel/icelake_rvp ?

These two are not much active system at this stage. So, I would request let's use this current existing code base and patch, later if required we will surely add the required soc_power_limits_cofnig info for these systems.

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41236 )

Change subject: icelake: remove unused processor power limits configuration
......................................................................

Patch Set 2: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/41236/1/src/soc/intel/icelake/chip.... 
File src/soc/intel/icelake/chip.h:

https://review.coreboot.org/c/coreboot/+/41236/1/src/soc/intel/icelake/chip.... 
PS1, Line 175: 	/* Intel Speed Shift Technology */
> These two are not much active system at this stage. […]

Ack

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41236 )

Change subject: icelake: remove unused processor power limits configuration
......................................................................

icelake: remove unused processor power limits configuration

Remove unused processor power limit configuration parameter
and function call based on common code base support for
Intel Icelake SoC based platform.

BRANCH=None
BUG=None
TEST=Built for icelake based dragonegg board.

Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8
Signed-off-by: Sumeet R Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41236
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/include/soc/cpu.h
2 files changed, 0 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index d67a70c..2b190cd 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -171,8 +171,6 @@
    /* HeciEnabled decides the state of Heci1 at end of boot
     * Setting to 0 (default) disables Heci1 and hides the device from OS */
    uint8_t HeciEnabled;
-	/* PL2 Override value in Watts */
-	uint32_t tdp_pl2_override;
    /* Intel Speed Shift Technology */
    uint8_t speed_shift_enable;
    /* Enable VR specific mailbox command
diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h
index e0f3e52..a231333 100644
--- a/src/soc/intel/icelake/include/soc/cpu.h
+++ b/src/soc/intel/icelake/include/soc/cpu.h
@@ -30,7 +30,4 @@
    C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
    			      (IRTL_1024_NS >> 10))

-/* Configure power limits for turbo mode */
-void set_power_limits(u8 power_limit_1_time);
-
 #endif

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41236 )

Change subject: icelake: remove unused processor power limits configuration
......................................................................

Patch Set 3:

Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3658
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3657
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3656
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3655

Please note: This test is under development and might not be accurate at all!