Change in coreboot[master]: [UNTESTED] soc/amd/common/block/lpc/lpc: rework resource index handling

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62579 )

Change subject: [UNTESTED] soc/amd/common/block/lpc/lpc: rework resource index handling
......................................................................

[UNTESTED] soc/amd/common/block/lpc/lpc: rework resource index handling

Signed-off-by: Felix Held 
Change-Id: I38b2845c982e01f263e70e9639dc2d8a3a7f6925
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 13 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/62579/1

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 106ae1e..3cfe6f6 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -85,31 +85,36 @@
    setup_serirq();
 }

+/* pci_dev_read_resources might add up to 7 resources (6 BARs and ROM BAR) */
+#define LPC_FIRST_NONSTANDARD_RESOURCE_IDX	7
+
 static void lpc_read_resources(struct device *dev)
 {
+	unsigned int idx;
    struct resource *res;

/* Get the normal pci resources of this device */
    pci_dev_read_resources(dev);

+	/* Add a memory resource for the SPI BAR with LPC_FIRST_NONSTANDARD_RESOURCE_IDX as
+	   resource index so we can easily find it again in lpc_set_resources below. */
+	idx = LPC_FIRST_NONSTANDARD_RESOURCE_IDX;
+	fixed_mem_resource(dev, idx++, SPI_BASE_ADDRESS / KiB, 1, IORESOURCE_SUBTRACTIVE);
+
    /* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res = new_resource(dev, idx++);
    res->base = 0;
    res->size = 0x1000;
    res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
    	     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res = new_resource(dev, idx++);
    res->base = FLASH_BASE_ADDR;
    res->size = CONFIG_ROM_SIZE;
    res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
    	     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

-	/* Add a memory resource for the SPI BAR. */
-	fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / KiB, 1,
-			IORESOURCE_SUBTRACTIVE);
-
-	res = new_resource(dev, 3); /* IOAPIC */
+	res = new_resource(dev, idx++); /* IOAPIC */
    res->base = IO_APIC_ADDR;
    res->size = 0x00001000;
    res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
@@ -123,7 +128,7 @@
    u32 spi_enable_bits;

/* Special case. The SpiRomEnable and other enables should STAY set. */
-	res = find_resource(dev, 2);
+	res = find_resource(dev, LPC_FIRST_NONSTANDARD_RESOURCE_IDX);
    spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER);
    spi_enable_bits &= SPI_BASE_ALIGNMENT - 1;
    pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER,