Change in coreboot[master]: mb/google/guybrush: Update bootblock power-on timings for PCIe
Attention is currently required from: Raul Rangel, Rob Barnes. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52868 )
Change subject: mb/google/guybrush: Update bootblock power-on timings for PCIe ......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52868/comment/506efa49_60868e33 PS6, Line 15: On v1 of guybrush, the PCIe reset line : also resets EC communication, so it must be brought up immediately on : that version.
We no longer need to support this case since we require rework #22 for S0i3 to work. […]
Let's discuss this. I think it's needed. Not everyone cares about S0i3 and not everyone has rework22.
File src/mainboard/google/guybrush/bootblock.c:
https://review.coreboot.org/c/coreboot/+/52868/comment/50c25487_c28ea5cf PS6, Line 20: timeout_us != GET_TIMER
Can we make timeout_sw global and call `stopwatch_init_usecs_expire(&timeout_sw, FC350_PCIE_INIT_DEL […]
Sure we could. But I'd rather not. Is there a problem with doing it in a function?
https://review.coreboot.org/c/coreboot/+/52868/comment/34088028_44db91db PS6, Line 25: stopwatch_expired
stopwatch_expired calls stopwatch_tick
Thanks. Will remove.
https://review.coreboot.org/c/coreboot/+/52868/comment/e656e720_b1e1af0f PS6, Line 76: 20ms
Bootblock seems to be taking 3ms: […]
I agree that it's taking 3 ms, but that's why the delay only happens when we're not using PSP_Verstage. Since the normal flow will be to use PSP verstage, there won't be any delay here. Because of that, there's no need to move this.
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52868/comment/734a46c7_6967d218 PS6, Line 244: Unset
Deasseert?
Sure.
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Martin Roth (Code Review)