[L] Change in coreboot[main]: soc/intel/common: Refactor BERT generation flow for crashlog

[Pratikkumar V Prajapati (Code Review)]

Hello Pratikkumar Prajapati,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/78257?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/common: Refactor BERT generation flow for crashlog
......................................................................

soc/intel/common: Refactor BERT generation flow for crashlog

With earlier flow, a chunk of CBMEM region was allocated for
each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM.
Then entire SRAM content was copied to dedicated CBMEM
region. Later in acpi_bert.c, the BERT table was getting
created for each chunk of CBMEM. This flow was not considering
creating separate entries for each region of crashlog records.
It resulted in only the first entry getting decoded from each SRAM.

New flow aims to fix this issue. With new flow, a simple singly
linked list is created to store each region of crashlog records
from all SRAMs. The crashlog data is not copied to CBMEM. The
nodes are allocated dynamically and then copied to ACPI BERT table
and then freed. This flow also makes the overall crashlog code
much simpler.

BUG=b:298234592
TEST= TBD.

Change-Id: I43bb61485b77d786647900ca284b7f492f412aee
Signed-off-by: Pratikkumar Prajapati 
---
M src/soc/intel/common/block/acpi/acpi_bert.c
M src/soc/intel/common/block/crashlog/crashlog.c
M src/soc/intel/common/block/include/intelblocks/crashlog.h
3 files changed, 148 insertions(+), 190 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/78257/2