Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Sukumar Ghorai, Tarun.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email )
Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table ......................................................................
Patch Set 4:
(3 comments)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/78164/comment/bfe5269b_3aa6b622 : PS4, Line 456: CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC CONFIG(SOC_INTEL_SLP_S0_FREQ_TSC)
https://review.coreboot.org/c/coreboot/+/78164/comment/7110521d_eebf0220 : PS4, Line 461: another thought why not set the macro based on the CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC value? and default value for CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC is zero unless overrides by the SoC Kconfig ?
#define ACPI_LPIT_CTR_FREQ_TSC CONFIG_SOC_INTEL_SLP_S0_FREQ_TSC
File src/soc/intel/common/block/acpi/lpit.c:
https://review.coreboot.org/c/coreboot/+/78164/comment/d17abf85_8aef37f2 : PS3, Line 34: MSR value return in usec
MSR 0x632 is for all Intel Core SoCs Package C-10 entry counter and give is mico-sec and hence we must not apply the TSC frequency,
are you saying the value should be in usec hence it's better to set it zero ?
if yes, then why are you overriding this macro ACPI_LPIT_CTR_FREQ_TSC using Kconfig ?
https://review.coreboot.org/c/coreboot/+/78164/4/src/include/acpi/acpi.h#457
looking at the overrides in rex (MTL). I'm confused and need to understand things better
1. setting ACPI_LPIT_CTR_FREQ_TSC based on kconfig should be managed in different CL 2. MTL overriding ACPI_LPIT_CTR_FREQ_TSC using Kconfig
3. who is the user of ACPI_LPIT_CTR_FREQ_TSC if you are hardcoding the counter_frequency to zero.