Change in coreboot[master]: mb/google/brya/var/crota: setting for codec reset pin in overridetree

[Terry Chen (Code Review)]

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64043 )

Change subject: mb/google/brya/var/crota: setting for codec reset pin in overridetree
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mb/google/brya/var/crota: setting for codec reset pin in overridetree

Crota360 is using a Cirrus CS42L42 for its audio codec; it
requires the reset pin to be deasserted in ramstage for proper
power sequencing.

BUG=b:230074351
BRANCH=none
TEST=build coreboot without error

Signed-off-by: Terry Chen 
Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e
---
M src/mainboard/google/brya/variants/crota/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/64043/1

diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index 20820ac..d96e0f1 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -131,7 +131,7 @@
    	device ref i2c0 on
    		chip drivers/i2c/cs42l42
    			register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B15)"
    			register "ts_inv" = "true"
    			register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
    			register "ts_dbnc_fall" = "FALL_DEB_0_MS"