Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage

[Angel Pons (Code Review)]

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Yu-Ping Wu, Jianjun Wang.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 )

Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage
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Patch Set 9: Code-Review+1

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62359/comment/4ea1b33a_dc3d1a5a 
PS9, Line 14: 100ms
Is there a way to ensure this minimum delay of 100ms is still met? coreboot could be too fast in some cases (try reducing/disabling logging to UART).