Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43732 )
Change subject: nb/intel/ironlake: Add definition for SAD PCI device ......................................................................
nb/intel/ironlake: Add definition for SAD PCI device
Let's hope this cheers up the poor System Address Decoder device.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/ironlake/smi.c 6 files changed, 20 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43732/1
diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 7289e92..1fa7267 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -13,7 +13,7 @@ u32 pciexbar_reg; int max_buses;
- pciexbar_reg = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x50); + pciexbar_reg = pci_read_config32(QPI_SAD, 0x50);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index d40b0b5..50e7adb 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -2,9 +2,10 @@
#include <arch/bootblock.h> #include <device/pci_ops.h> +#include "ironlake.h"
void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); + pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, 0x54, 0); } diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b68d954..2154478 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -25,13 +25,13 @@ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
/* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(0), 0x30); + pci_write_config8(QPI_SAD, QPD0F1_PAM(1), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(2), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(3), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(4), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(5), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(6), 0x33);
printk(BIOS_DEBUG, " done.\n"); } diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 5a1d52e..dd8de97 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -48,8 +48,10 @@ #include "hostbridge_regs.h"
/* - * QPI D0:F1 + * SAD - System Address Decoder */ +#define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) + #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 3d27762..1017be4 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1337,9 +1337,9 @@ MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); for (i = 0; i < 8; i++) { - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i, + pci_write_config32(QPI_SAD, 0x80 + 4 * i, (info->total_memory_mb - 64) | !i | 2); - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0); + pci_write_config32(QPI_SAD, 0xc0 + 4 * i, 0); } }
@@ -1412,7 +1412,7 @@ memory_map[2] = touud | 1; quickpath_reserved = 0;
- u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68); + u32 t = pci_read_config32(QPI_SAD, 0x68);
gav(t);
@@ -1452,10 +1452,10 @@ memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = MAX(current_limit, memory_map[i] & ~1); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, + pci_write_config32(QPI_SAD, 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0); + pci_write_config32(QPI_SAD, 4 * i + 0xc0, 0); } }
diff --git a/src/northbridge/intel/ironlake/smi.c b/src/northbridge/intel/ironlake/smi.c index 9ffcb99..0604d13 100644 --- a/src/northbridge/intel/ironlake/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -11,5 +11,5 @@
void northbridge_write_smram(u8 smram) { - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_write_config8(QPI_SAD, QPD0F1_SMRAM, smram); }
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43732 )
Change subject: nb/intel/ironlake: Add definition for SAD PCI device ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43732 )
Change subject: nb/intel/ironlake: Add definition for SAD PCI device ......................................................................
nb/intel/ironlake: Add definition for SAD PCI device
Let's hope this cheers up the poor System Address Decoder device.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/ironlake/smi.c 6 files changed, 20 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 7289e92..1fa7267 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -13,7 +13,7 @@ u32 pciexbar_reg; int max_buses;
- pciexbar_reg = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x50); + pciexbar_reg = pci_read_config32(QPI_SAD, 0x50);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index d40b0b5..50e7adb 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -2,9 +2,10 @@
#include <arch/bootblock.h> #include <device/pci_ops.h> +#include "ironlake.h"
void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); + pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, 0x54, 0); } diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b68d954..2154478 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -25,13 +25,13 @@ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
/* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(0), 0x30); + pci_write_config8(QPI_SAD, QPD0F1_PAM(1), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(2), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(3), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(4), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(5), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(6), 0x33);
printk(BIOS_DEBUG, " done.\n"); } diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 5a1d52e..dd8de97 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -48,8 +48,10 @@ #include "hostbridge_regs.h"
/* - * QPI D0:F1 + * SAD - System Address Decoder */ +#define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1) + #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index c30a5dc..ecfbd8a 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1337,9 +1337,9 @@ MCHBAR16_OR(0x612, 0x100); MCHBAR16_OR(0x214, 0x3E00); for (i = 0; i < 8; i++) { - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i, + pci_write_config32(QPI_SAD, 0x80 + 4 * i, (info->total_memory_mb - 64) | !i | 2); - pci_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0); + pci_write_config32(QPI_SAD, 0xc0 + 4 * i, 0); } }
@@ -1412,7 +1412,7 @@ memory_map[2] = touud | 1; quickpath_reserved = 0;
- u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68); + u32 t = pci_read_config32(QPI_SAD, 0x68);
gav(t);
@@ -1452,10 +1452,10 @@ memory_map[1] = 4096; for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = MAX(current_limit, memory_map[i] & ~1); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, + pci_write_config32(QPI_SAD, 4 * i + 0x80, (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); - pci_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0); + pci_write_config32(QPI_SAD, 4 * i + 0xc0, 0); } }
diff --git a/src/northbridge/intel/ironlake/smi.c b/src/northbridge/intel/ironlake/smi.c index 9ffcb99..0604d13 100644 --- a/src/northbridge/intel/ironlake/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -11,5 +11,5 @@
void northbridge_write_smram(u8 smram) { - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_write_config8(QPI_SAD, QPD0F1_SMRAM, smram); }
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Patrick Georgi (Code Review)