Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer.
Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74095 )
Change subject: mb/google/myst: First pass GPIO configuration for Myst ......................................................................
Patch Set 10:
(7 comments)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/6c56aff9_5e67ee70 PS8, Line 79: * SPI_SOC_CLK_TCHSCR_R */
SOC_CLK_FPMCU_R since all TS are I2C based for now. […]
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/4dcd24dc_25bde526 PS8, Line 83: /* SPI_SOC_CS_TCHSCR_R_L */
Same comment as in line 79
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/18500a66_df59e631 PS8, Line 107: SSD
WLAN
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/2125a0c3_2f128c18 PS8, Line 109: /* SPI_SOC_DO_TCHSCR_DI_R */ : PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), : /* SPI_SOC_DO_TCHSCR_DO_R */ : PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE)
These are FPMCU only for now. Same comment as in line 79.
Should also get EE's to update schematic nets
https://review.coreboot.org/c/coreboot/+/74095/comment/064f7041_f127bcb8 PS8, Line 123: WLAN
WWAN
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/cabd2ff9_4af5be00 PS8, Line 127:
/ SSD
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/7ea6106c_645ee6f9 PS8, Line 142: PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
Same comment as in line 79
Done
-
Jon Murphy (Code Review)