Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths

[Jamie Ryu (Code Review)]

Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Wonkyu Kim, Paul Menzel, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Nick Vaccaro, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44557

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
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soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths

Add the FSP UPDs for the chipset minimum assertion widths and
Power cycle duration to the chip options which can be configured
per mainboard.

* PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
* PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
* PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
* PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
* PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
* Check to avoid violating the PCH EDS recommendation for the
  PchPmPwrCycDur setting.

BUG=b:159108661

Signed-off-by: Jamie Ryu 
Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 70 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44557/2