New patch to review for coreboot: fsp1_0: Update Kconfig for symbols not depending on FSP binary

[Martin Roth]

Martin Roth ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12461

-gerrit

commit e208d629a990c4dfe26430f4ba60e548f4d29318
Author: Martin Roth 
Date:   Wed Nov 18 16:07:54 2015 -0700

fsp1_0: Update Kconfig for symbols not depending on FSP binary

There were several symbols that were inside the 'if HAVE_FSP_BIN' that
    don't really depend on having the FSP binary.  In theory, we should be
    able to build a coreboot rom and add the FSP binary later.  This doesn't
    always work in practice, but this is a step in that direction.

This also fixes a Kconfig warning for Rangeley.

Change-Id: I327d8fe5231d7de25f2a74b8a193deb47e4c5ee1
    Signed-off-by: Martin Roth 
---
 src/drivers/intel/fsp1_0/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
index 36bfa7c..cb83f83 100644
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ b/src/drivers/intel/fsp1_0/Kconfig
@@ -48,6 +48,8 @@ config FSP_LOC
      value that is set in the FSP binary.  If the FSP needs to be moved,
      rebase the FSP with Intel's BCT (tool).

+endif #HAVE_FSP_BIN
+
 config ENABLE_FSP_FAST_BOOT
    bool "Enable Fast Boot"
    select ENABLE_MRC_CACHE
@@ -92,8 +94,6 @@ config VIRTUAL_ROM_SIZE
      the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
      size is 16 MB.

-endif #HAVE_FSP_BIN
-
 config CACHE_ROM_SIZE_OVERRIDE
    hex "Cache ROM Size"
    default CBFS_SIZE