Change in coreboot[master]: soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code
......................................................................

soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code

This patch includes common romstage code to setup the console
and load postcar.

Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/romstage/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35109/1

diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
index 75d7985..33d9629 100644
--- a/src/soc/intel/cannonlake/romstage/Makefile.inc
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -13,6 +13,7 @@
 # GNU General Public License for more details.
 #

+romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += fsp_params.c
 romstage-y += systemagent.c

[Subrata Banik (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35109

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code
......................................................................

soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code

This patch includes common romstage code to setup the console
and load postcar.

Fix booting regression issue on CML-Hatch introduced by CB:34893

Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/romstage/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35109/2

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code
......................................................................

Patch Set 2:

Ahh crap, there is a weak .car_stage_entry definition. Same fix for apoololake, icelake and denverton_ns.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/cannonlake: Use common cpu/intel/car/romstage.c code
......................................................................

Patch Set 2: Code-Review+2
> Patch Set 2:
>
> Ahh crap, there is a weak .car_stage_entry definition. Same fix for apoololake, icelake and denverton_ns.

Subrata - are you planning on pushing changes for the rest of the affected platforms as well? It might make sense to push it as a single CL.

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Subrata Banik (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35109

to look at the new patch set (#3).

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code

This patch includes common romstage code to setup the console
and load postcar.

Fix booting regression issue on all latest IA-SOC introduced by CB:34893

Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik 
---
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/cannonlake/romstage/Makefile.inc
M src/soc/intel/denverton_ns/Makefile.inc
M src/soc/intel/icelake/romstage/Makefile.inc
M src/soc/intel/skylake/romstage/Makefile.inc
5 files changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35109/3

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

Patch Set 3:
> Patch Set 2: Code-Review+2
> > Patch Set 2:
> >
> > Ahh crap, there is a weak .car_stage_entry definition. Same fix for apoololake, icelake and denverton_ns.
>
> Subrata - are you planning on pushing changes for the rest of the affected platforms as well? It might make sense to push it as a single CL.

Done

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Subrata Banik (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Vanny E, build bot (Jenkins), Furquan Shaikh, David Guckian, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35109

to look at the new patch set (#4).

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code

This patch includes common romstage code to setup the console
and load postcar.

Fix booting regression issue on all latest IA-SOC introduced by CB:34893

Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik 
---
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/cannonlake/romstage/Makefile.inc
M src/soc/intel/denverton_ns/Makefile.inc
M src/soc/intel/icelake/romstage/Makefile.inc
M src/soc/intel/skylake/romstage/Makefile.inc
5 files changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35109/4

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c...

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35109 )

Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code
......................................................................

soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c code

This patch includes common romstage code to setup the console
and load postcar.

Fix booting regression issue on all latest IA-SOC introduced by CB:34893

Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109
Tested-by: build bot (Jenkins) 
Reviewed-by: Ronak Kanabar 
Reviewed-by: Maulik V Vaghela 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/cannonlake/romstage/Makefile.inc
M src/soc/intel/denverton_ns/Makefile.inc
M src/soc/intel/icelake/romstage/Makefile.inc
M src/soc/intel/skylake/romstage/Makefile.inc
5 files changed, 5 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved
  Ronak Kanabar: Looks good to me, approved

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 60b1a3c..41faf72 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -21,6 +21,7 @@
 bootblock-y += uart.c

romstage-y += car.c
+romstage-y += ../../../cpu/intel/car/romstage.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gspi.c
 romstage-y += heci.c
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
index 75d7985..33d9629 100644
--- a/src/soc/intel/cannonlake/romstage/Makefile.inc
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -13,6 +13,7 @@
 # GNU General Public License for more details.
 #

+romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += fsp_params.c
 romstage-y += systemagent.c
diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc
index f01fadb..10bb665 100644
--- a/src/soc/intel/denverton_ns/Makefile.inc
+++ b/src/soc/intel/denverton_ns/Makefile.inc
@@ -36,6 +36,7 @@

romstage-y += memmap.c
 romstage-y += reset.c
+romstage-y += ../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += tsc_freq.c
 romstage-y += gpio_dnv.c
diff --git a/src/soc/intel/icelake/romstage/Makefile.inc b/src/soc/intel/icelake/romstage/Makefile.inc
index 28e7ead..baa4d46 100644
--- a/src/soc/intel/icelake/romstage/Makefile.inc
+++ b/src/soc/intel/icelake/romstage/Makefile.inc
@@ -14,5 +14,6 @@
 #

romstage-y += fsp_params.c
+romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index e929eba..7bb9d4b 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,4 +1,4 @@
-romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c
+romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
 romstage-y += systemagent.c