[M] Change in coreboot[master]: [TEST-ONLY] check ibecc

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73346 )

Change subject: [TEST-ONLY] check ibecc
......................................................................

[TEST-ONLY] check ibecc

Signed-off-by: Ravi Sarawadi 
Change-Id: Idcd3dfb3a48cac7b187e8e27a8abac9d4bbe2a6b
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/romstage/fsp_params.c
4 files changed, 62 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/73346/1

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index a0eeaea..7727272 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -118,4 +118,11 @@
 config HAVE_SLP_S0_GATE
    def_bool n

+config ENABLE_IBECC
+	bool "Enable IBECC"
+	help
+	  Enables In Band Error Correction Code. It's only needed for endurance testing
+	  and therefore not always required.
+	default n
+
 endif # BOARD_GOOGLE_REX_COMMON
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 9a71e95..8f3ff92 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -42,6 +42,10 @@
    # Set on-board graphics as primary display
    register "skip_ext_gfx_scan" = "1"

+	# Enable Ibecc
+	register "ibecc.enable" = "CONFIG(ENABLE_IBECC)"
+	register "ibecc.mode" = "CONFIG(ENABLE_IBECC) ? IBECC_MODE_ALL : IBECC_MODE_NONE"
+
    register "serial_io_uart_mode" = "{
    	[PchSerialIoIndexUART0] = PchSerialIoPci,
    	[PchSerialIoIndexUART1] = PchSerialIoDisabled,
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 9bafb22..e7b3f21 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -17,6 +17,25 @@
 #include <soc/usb.h>
 #include <stdint.h>

+/* Define config parameters for In-Band ECC (IBECC). */
+#define MAX_IBECC_REGIONS	8
+
+/* In-Band ECC Operation Mode */
+enum ibecc_mode {
+	IBECC_MODE_PER_REGION,
+	IBECC_MODE_NONE,
+	IBECC_MODE_ALL
+};
+
+struct ibecc_config {
+	bool enable;
+	enum ibecc_mode mode;
+	bool range_enable[MAX_IBECC_REGIONS];
+	uint16_t range_base[MAX_IBECC_REGIONS];
+	uint16_t range_mask[MAX_IBECC_REGIONS];
+	/* add ECC error injection if needed by a mainboard */
+};
+
 /* Types of different SKUs */
 enum soc_intel_meteorlake_power_limits {
    MTL_P_POWER_LIMITS_1,
@@ -120,6 +139,9 @@
    /* TCC activation offset */
    uint32_t tcc_offset;

+	/* In-Band ECC (IBECC) configuration */
+	struct ibecc_config ibecc;
+
    /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
     * When enabled memory will be training at two different frequencies.
     * 0:Disabled, 1:Enabled
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index ec5a3af..bc0c373 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -287,6 +287,24 @@
    }
 }

+static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	/* In-Band ECC configuration */
+	if (config->ibecc.enable) {
+		m_cfg->Ibecc = config->ibecc.enable;
+		m_cfg->IbeccOperationMode = config->ibecc.mode;
+		if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) {
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable,
+				       config->ibecc.range_enable);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeBase,
+				       config->ibecc.range_base);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeMask,
+				       config->ibecc.range_mask);
+		}
+	}
+}
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
    	const struct soc_intel_meteorlake_config *config)
 {
@@ -308,6 +326,7 @@
    	fill_fspm_usb4_params,
    	fill_fspm_vtd_params,
    	fill_fspm_trace_params,
+		fill_fspm_ibecc_params,
    };

for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)