New patch to review for coreboot: gru: Increase SPI speed to 33MHz

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16708

-gerrit

commit 0f027f52bd50d0fe63b56bf514dd0feaf47ab6e7
Author: Simon Glass 
Date:   Sun Sep 4 18:56:46 2016 -0600

gru: Increase SPI speed to 33MHz

Increase the SPI bus speed to speed up boot time. The maximum supported
    speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed,
    given the clock parents.

BUG=chrome-os-partner:56556
    BRANCH=none
    TEST=boot on gru and see that things still work correctly. Total time
    spent on reading from SPI reduces from 185ms to 141ms.

Change-Id: I71436c9e343b18360fa63d528dea5cfcfbc831e6
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: d7576f6e53e407af61160be142c3d589e864a8cf
    Original-Change-Id: I55a19f523817862e081d23469e94fd795456dd67
    Original-Signed-off-by: Simon Glass 
    Original-Reviewed-on: https://chromium-review.googlesource.com/381313
    Original-Commit-Ready: Julius Werner 
    Original-Tested-by: Simon Glass 
    Original-Reviewed-by: Julius Werner 
---
 src/mainboard/google/gru/bootblock.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 6598dfe..c630b2d 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -82,7 +82,8 @@ void bootblock_mainboard_init(void)
    /* Set pinmux and configure spi flashrom. */
    write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
    write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
-	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz);
+	rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33000*KHz);
+	rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5);

/* Set pinmux and configure EC SPI. */
    write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);