Change in coreboot[master]: mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47255 )

Change subject: mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device
......................................................................

mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device

There is an issue with the storage device being mis-detected on exit
from S0ix which is causing the root device to disappear if the power
is actually turned off via RTD3.

To work around this read the RX state of the pin and apply the IOSSTATE
setting to drive a 0 or 1 back to the internal controller.  This will
ensure the device is detected the same on resume as on initial boot.

BUG=b:171993054
TEST=boot on volteer with PCIe NVMe and SATA SSD installed in the M.2
slot and ensure this pin is configured appropriately.  Additionally
test with PCIe RTD3 enabled to ensure suspend/resume works reliably.

Signed-off-by: Duncan Laurie 
Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78
---
M src/mainboard/google/volteer/mainboard.c
1 file changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47255/1

diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index acba972..ea4374d 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -7,6 +7,8 @@
 #include <drivers/spi/tpm/tpm.h>
 #include <ec/ec.h>
 #include <fw_config.h>
+#include <gpio.h>
+#include <intelblocks/gpio.h>
 #include <security/tpm/tss.h>
 #include <soc/gpio.h>
 #include <soc/pci_devs.h>
@@ -126,6 +128,25 @@
    override_pads = variant_override_gpio_table(&override_num);

gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
+
+	/*
+	 * Check SATAXPCIE1 (GPP_A12) RX status to determine if SSD is NVMe or SATA and set
+	 * the IOSSTATE RX field to drive 0 or 1 back to the internal controller to ensure
+	 * the attached device is not mis-detected on resume from S0ix.
+	 */
+	if (gpio_get(GPP_A12)) {
+		const struct pad_config gpio_pedet_nvme[] = {
+			PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx1),
+		};
+		gpio_configure_pads(gpio_pedet_nvme, ARRAY_SIZE(gpio_pedet_nvme));
+		printk(BIOS_INFO, "SATAXPCIE1 indicates PCIe NVMe is present\n");
+	} else {
+		const struct pad_config gpio_pedet_sata[] = {
+			PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx0),
+		};
+		gpio_configure_pads(gpio_pedet_sata, ARRAY_SIZE(gpio_pedet_sata));
+		printk(BIOS_INFO, "SATAXPCIE1 indicates SATA SSD is present\n");
+	}
 }

void mainboard_silicon_init_params(FSP_S_CONFIG *params)

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47255 )

Change subject: mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device
......................................................................

Patch Set 1: Code-Review+1

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47255 )

Change subject: mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device
......................................................................

Patch Set 1: Code-Review+2

KEEPER, neat 😊

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47255 )

Change subject: mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device
......................................................................

mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device

There is an issue with the storage device being mis-detected on exit
from S0ix which is causing the root device to disappear if the power
is actually turned off via RTD3.

To work around this read the RX state of the pin and apply the IOSSTATE
setting to drive a 0 or 1 back to the internal controller.  This will
ensure the device is detected the same on resume as on initial boot.

BUG=b:171993054
TEST=boot on volteer with PCIe NVMe and SATA SSD installed in the M.2
slot and ensure this pin is configured appropriately.  Additionally
test with PCIe RTD3 enabled to ensure suspend/resume works reliably.

Signed-off-by: Duncan Laurie 
Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47255
Tested-by: build bot (Jenkins) 
Reviewed-by: Shreesh Chhabbi 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/volteer/mainboard.c
1 file changed, 21 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Shreesh Chhabbi: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 0850e74..ea9e08f 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -7,6 +7,8 @@
 #include <drivers/spi/tpm/tpm.h>
 #include <ec/ec.h>
 #include <fw_config.h>
+#include <gpio.h>
+#include <intelblocks/gpio.h>
 #include <security/tpm/tss.h>
 #include <soc/gpio.h>
 #include <soc/pci_devs.h>
@@ -136,6 +138,25 @@
    override_pads = variant_override_gpio_table(&override_num);

gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
+
+	/*
+	 * Check SATAXPCIE1 (GPP_A12) RX status to determine if SSD is NVMe or SATA and set
+	 * the IOSSTATE RX field to drive 0 or 1 back to the internal controller to ensure
+	 * the attached device is not mis-detected on resume from S0ix.
+	 */
+	if (gpio_get(GPP_A12)) {
+		const struct pad_config gpio_pedet_nvme[] = {
+			PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx1),
+		};
+		gpio_configure_pads(gpio_pedet_nvme, ARRAY_SIZE(gpio_pedet_nvme));
+		printk(BIOS_INFO, "SATAXPCIE1 indicates PCIe NVMe is present\n");
+	} else {
+		const struct pad_config gpio_pedet_sata[] = {
+			PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx0),
+		};
+		gpio_configure_pads(gpio_pedet_sata, ARRAY_SIZE(gpio_pedet_sata));
+		printk(BIOS_INFO, "SATAXPCIE1 indicates SATA SSD is present\n");
+	}
 }

void mainboard_silicon_init_params(FSP_S_CONFIG *params)