Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Julius Werner, Kyösti Mälkki, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55502 )
Change subject: [RFC,WIP] ChromeOS: Create pseudo-device ACPI NVS ......................................................................
Patch Set 5:
(2 comments)
File src/vendorcode/google/chromeos/acpi/gnvs.asl:
https://review.coreboot.org/c/coreboot/+/55502/comment/48fcbaa3_9d16840f PS5, Line 4: * the mainboard's chromeos.asl
Drop the word mainboard's ?
yes
https://review.coreboot.org/c/coreboot/+/55502/comment/b944fafc_2b7e5370 PS5, Line 12: Field (CNVS, ByteAcc, NoLock, Preserve) : { : VBT0, 32, // 0x000 - Boot Reason : VBT1, 32, // 0x004 - Active Main Firmware : VBT2, 32, // 0x008 - Active EC Firmware : VBT3, 16, // 0x00c - CHSW : VBT4, 2048, // 0x00e - HWID : VBT5, 512, // 0x10e - FWID : VBT6, 512, // 0x14e - FRID : VBT7, 32, // 0x18e - active main firmware type : VBT8, 32, // 0x192 - Recovery Reason : VBT9, 32, // 0x196 - FMAP base address : CHVD, 24576, // 0x19a - VDAT space filled by verified boot : VBTA, 32, // 0xd9a - pointer to smbios FWID : MEHH, 256, // 0xd9e - Management Engine Hash : RMOB, 32, // 0xdbe - RAM oops base address : RMOL, 32, // 0xdc2 - RAM oops length : ROVP, 32, // 0xdc6 - pointer to RO_VPD : ROVL, 32, // 0xdca - size of RO_VPD : RWVP, 32, // 0xdce - pointer to RW_VPD : RWVL, 32, // 0xdd2 - size of RW_VPD : // 0xdd6 : }
There is no real requirement for separate gnvs. […]
Ack
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Lance Zhao (Code Review)