Change in coreboot[master]: soc/intel/xeon_sp: Add initial PCH lockdown

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48509 )

Change subject: soc/intel/xeon_sp: Add initial PCH lockdown
......................................................................

soc/intel/xeon_sp: Add initial PCH lockdown

TESTED: on ocp/deltalake

Change-Id: I287819471762e2eba038597868f8d10935ea9fd4
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/common/pch/Kconfig
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/lpc.c
3 files changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48509/1

diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index cca65d6..1125f29 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -12,10 +12,17 @@

if SOC_INTEL_COMMON_PCH_BASE

+config SOC_INTEL_NO_ALL_PCH_OPTIONS
+	bool
+	help
+	  Select this if you want to be more selective about the common code
+	  you wish to include.
+
 source "src/soc/intel/common/pch/*/Kconfig"

config PCH_SPECIFIC_OPTIONS
-	def_bool y
+	bool
+	default y if !SOC_INTEL_NO_ALL_PCH_OPTIONS
    select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
    select SOC_INTEL_COMMON_BLOCK_CSE
    select SOC_INTEL_COMMON_BLOCK_DSP
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 2028a5e..c573ebe 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -44,6 +44,7 @@
    select SOC_INTEL_COMMON_BLOCK_LPC
    select SOC_INTEL_COMMON_BLOCK_RTC
    select SOC_INTEL_COMMON_BLOCK_SPI
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
    select SOC_INTEL_COMMON_BLOCK_FAST_SPI
    select SOC_INTEL_COMMON_BLOCK_GPIO
    select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
@@ -54,6 +55,9 @@
    select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_TCO
+	select SOC_INTEL_COMMON_PCH_BASE
+	select SOC_INTEL_COMMON_PCH_LOCKDOWN
+	select SOC_INTEL_NO_ALL_PCH_OPTIONS
    select TSC_MONOTONIC_TIMER
    select UDELAY_TSC
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
index 3169545..c3d7092 100644
--- a/src/soc/intel/xeon_sp/lpc.c
+++ b/src/soc/intel/xeon_sp/lpc.c
@@ -4,6 +4,7 @@
 #include <arch/ioapic.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
+#include <intelpch/lockdown.h>
 #include <soc/iomap.h>
 #include <soc/pcr_ids.h>

@@ -50,3 +51,7 @@
 void pch_lpc_soc_fill_io_resources(struct device *dev)
 {
 }
+
+void soc_lockdown_config(int chipset_lockdown)
+{
+}